A power- and area-efficient SRAM core architecture with segmentation-free and horizontal/vertical accessibility for super-parallel video processing

IEICE Transactions on Electronics

Volumn E89-C, Issue 11, 2006, Pages 1629-1636

  Miyakoshi, Junichi ^a   Murachi, Yuichiro ^a   Ishihara, Tomokazu ^a   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a  

^a KOBE UNIVERSITY   (Japan)

Author keywords

H.264; Image signal processing; Low power; MPEG; Parallel processing; SRAM

Indexed keywords

DECODING; IMAGE SEGMENTATION; MOTION ESTIMATION; PARALLEL PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE;

H.264; IMAGE SIGNAL PROCESSING; MPEG; SEGMENTATION FREE ACCESS;

COMPUTER ARCHITECTURE;

EID: 33845584846     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e89-c.11.1629     Document Type: Article

References (5)

1. ITU-T Rec.H.264|ISO/IEC 14496-10AVC,"DraftITU-Trecommendation and final draft international standard of joint video specification," 2003.
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