Leakage power-aware clock skew scheduling: Converting stolen time into leakage power reduction

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 610-613

  Ni, Min ^a   Memik, Seda Ogrenci ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

Author keywords

Clock skew scheduling; Dual Vth; Gate sizing; Leakage power optimization

Indexed keywords

CLOCK SKEW SCHEDULING; DUAL-VTH; GATE SIZING; LEAKAGE POWER OPTIMIZATION;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; GATES (TRANSISTOR); INDUSTRIAL ENGINEERING; LOGIC CIRCUITS; SCHEDULING; TIMING DEVICES;

CLOCKS;

EID: 51549121627     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555890     Document Type: Conference Paper

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