Synthesis of nonzero clock skew circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 6, 2006, Pages 961-976

  Huang, Shih Hsu ^a,b   Nieh, Yow Tyng ^b  

^a IEEE   (Taiwan)

^b CHUNG YUAN CHRISTIAN UNIVERSITY   (Taiwan)

Author keywords

Logic synthesis; Performance optimization; Scheduling; Timing optimization

Indexed keywords

LOGIC SYNTHESIS; NONZERO CLOCK SKEW CIRCUITS; PERFORMANCE OPTIMIZATION; SEQUENTIAL TIMING OPTIMIZATION; TIMING OPTIMIZATION;

BENCHMARKING; CLOCKS; COMPUTATIONAL COMPLEXITY; OPTIMIZATION; POLYNOMIALS; SCHEDULING;

LOGIC CIRCUITS;

EID: 33646733848     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.855923     Document Type: Article

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