Fast generation of statistically-based worst-case modeling of on-chip interconnect

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 720-725

  Chang, Norman ^a   Kanevsky, Valery ^a   Nakagawa, O Sam ^a   Rahmat, Khalid ^a   Oh, Soo Young ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; MONTE CARLO METHODS;

CRITICAL NET ANALYSIS; STATISTICALLY BASED WORST CASE MODELING;

INTERCONNECTION NETWORKS;

EID: 0031377695     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)