Automatic synthesis of clock gating logic with controlled netlist perturbation

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 654-657

  Hurst, Aaron P ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clock gating; Dynamic power; Logic optimization; Low power

Indexed keywords

CLOCK GATING; DYNAMIC POWER; LOGIC OPTIMIZATION; LOW POWER;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; PERTURBATION TECHNIQUES;

CLOCKS;

EID: 51549104736     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555899     Document Type: Conference Paper

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