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Volumn , Issue , 2008, Pages 540-545

Merging nodes under sequential observability

Author keywords

Merge; Observable; Sequential; Synthesis

Indexed keywords

DESIGN AUTOMATION CONFERENCE; MERGE; OBSERVABLE; SEQUENTIAL; SYNTHESIS;

EID: 51549101677     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555875     Document Type: Conference Paper
Times cited : (17)

References (25)
  • 1
    • 51549093673 scopus 로고    scopus 로고
    • J. Baumgartner, Integrating FV Into Main-Stream Verification: The IBM Experience, Tutorial Given at FMCAD 2006.
    • J. Baumgartner, "Integrating FV Into Main-Stream Verification: The IBM Experience," Tutorial Given at FMCAD 2006.
  • 4
    • 0030646028 scopus 로고    scopus 로고
    • A. Kuehlmann and F. Krohm, Equivalence checking using cuts and heaps, DAC 1997.
    • A. Kuehlmann and F. Krohm, "Equivalence checking using cuts and heaps," DAC 1997.
  • 5
    • 0027832523 scopus 로고
    • Verification of large synthesized designs
    • D. Brand, "Verification of large synthesized designs," in ICCAD 1993.
    • (1993) ICCAD
    • Brand, D.1
  • 6
    • 0027839536 scopus 로고
    • HANNIBAL: An efficient tool for logic verificabased on recursive learning
    • W. Kunz, "HANNIBAL: An efficient tool for logic verificabased on recursive learning," in ICCAD 1993.
    • (1993) ICCAD
    • Kunz, W.1
  • 7
    • 51549089240 scopus 로고    scopus 로고
    • Logic optimization and equivalence checking by implication analysis
    • W. Kunz, D. Stoffel, and P. Menon, "Logic optimization and equivalence checking by implication analysis," in ICCAD 1997.
    • (1997) ICCAD
    • Kunz, W.1    Stoffel, D.2    Menon, P.3
  • 8
    • 84893713000 scopus 로고    scopus 로고
    • Using SAT in combinational equivalence checking
    • E. Goldberg, M.R. Prasad, and R.K. Brayton, "Using SAT in combinational equivalence checking," in DATE 2001.
    • (2001) DATE
    • Goldberg, E.1    Prasad, M.R.2    Brayton, R.K.3
  • 9
    • 84893813903 scopus 로고    scopus 로고
    • A circuit SAT solver with signal correlation guided learning
    • F. Lu, L.C. Wang, K.T. Cheng, and R.C.Y. Huang, "A circuit SAT solver with signal correlation guided learning," in DATE 2003.
    • DATE 2003
    • Lu, F.1    Wang, L.C.2    Cheng, K.T.3    Huang, R.C.Y.4
  • 11
    • 0034224829 scopus 로고    scopus 로고
    • Sequential equivalence checking based on structural similarities
    • July
    • C. van Eijk, "Sequential equivalence checking based on structural similarities," IEEE Trans. Computer-Aided Design, July 2000.
    • (2000) IEEE Trans. Computer-Aided Design
    • van Eijk, C.1
  • 16
    • 2542494639 scopus 로고    scopus 로고
    • SAT-based Verification without State Space Traversal
    • P. Bjesse and K. Claessen, "SAT-based Verification without State Space Traversal," in FMCAD 2000.
    • (2000) FMCAD
    • Bjesse, P.1    Claessen, K.2
  • 22
    • 57649214960 scopus 로고    scopus 로고
    • Niklas Een, Niklas Sorensson, MiniSat. http://www.cs.chalmers.se/Cs/ Research/FormalMethods/MiniSat/
    • MiniSat
    • Een, N.1    Sorensson, N.2
  • 23
    • 51549093047 scopus 로고    scopus 로고
    • Sun Microsystems, Processor Technology Resources - picoJava, http://www.sun.com/software/communitysource/processors/picojava.xml
    • Sun Microsystems, "Processor Technology Resources - picoJava," http://www.sun.com/software/communitysource/processors/picojava.xml
  • 24
    • 85165839765 scopus 로고    scopus 로고
    • A. Mishchenko, S. Chatterjee, and R.K. Brayton, DAC-aware AIG rewriting: A fresh look at combinational logic synthesis, in DAC 2006.
    • A. Mishchenko, S. Chatterjee, and R.K. Brayton, "DAC-aware AIG rewriting: A fresh look at combinational logic synthesis," in DAC 2006.
  • 25
    • 51549095474 scopus 로고    scopus 로고
    • P. Bjesse and J., Automatic Phase Abstraction for Formal Verification, in ICCAD 2005.
    • P. Bjesse and J., "Automatic Phase Abstraction for Formal Verification," in ICCAD 2005.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.