Robust chip-level clock tree synthesis for SOC designs

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 720-723

  Rajaram, Anand ^a   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Chip level CTS; Clock network; Physical design

Indexed keywords

CHIP-LEVEL CLOCK TREE; CHIP-LEVEL CTS; CLOCK NETWORK; DESIGN AUTOMATION CONFERENCE; PHYSICAL DESIGN;

ADAPTIVE SYSTEMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; TELECOMMUNICATION NETWORKS; TIME MEASUREMENT;

CLOCKS;

EID: 51549101270     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555913     Document Type: Conference Paper

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