A 65nm C64x+™ multi-core DSP platform for communications infrastructure

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 262-264

  Agarwala, Sanjive ^a   Rajagopal, Arjun ^a   Hill, Anthony ^a   Joshi, Mayur ^a   Mullinnlx, Steven ^a   Anderson, Timothy ^a   Damodaran, Raguram ^a   Nardini, Lewis ^a   Wiley, Paul ^a   Groves, Peter ^a   Apostol, John ^a   Gill, Michael ^a   Flores, Jose ^a   Chachad, Abhijeet ^a   Hales, Alan ^a   Chirca, Kai ^a   Panda, Krishna ^a   Venkatasubramanian, Rama ^a   Eyres, Patrick ^a   Velamuri, Rajasekhar ^a   Rajaram, Anand ^a   Krishnan, Manjeri ^a   Nelson, Johnathan ^a   Frade, Jose ^a   Rahman, Mujibur ^a   Mahmood, Nuruddin ^a   Naraslmha, Usha ^a   Sinha, Snehamay ^a   Krishnan, Sridhar ^a   Webster, William ^a   Bui, Due ^a   Moharil, Shriram ^a   Common, Neil ^a   Nair, Rejitha ^a   Ramanujam, Rajesh ^a   Ryan, Monica ^a   more..

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATION; BASE STATIONS; CMOS INTEGRATED CIRCUITS; INTEGRATION; TRANSISTORS;

CMOS INTEGRATION; MMAC; SINGLE CHIP;

DIGITAL SIGNAL PROCESSING;

EID: 34548822121     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373394     Document Type: Conference Paper

References (3)

1. C. Bittlestone, et al., "Architecting ASIC Libraries and Flows in the nm Era", Design Automation Conference, pp. 776-781, June, 2003.
2. A. Hill, et al., "Physical Datapath: Regularized Datapath Placement and Optimization Technology," SNUG, March, 2005.
3. Freescale MSC 8144 DSP, http://www.freescale.com/webapp/sps/site/ prod_summary.jsp?code=MSC8144