Residual stress distribution in stacked LSI chips mounted by flip chip technology

2006 International Conference on Electronic Materials and Packaging, EMAP

Volumn , Issue , 2006, Pages

  Ueta, Nobuki ^a   Miura, Hideo ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; ELECTRONIC EQUIPMENT MANUFACTURE; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; LSI CIRCUITS; PACKAGING MATERIALS; RESIDUAL STRESSES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; STRENGTH OF MATERIALS; STRESS CONCENTRATION; THERMAL EXPANSION; THERMAL SPRAYING; THICKNESS MEASUREMENT;

ELECTRONIC MATERIALS AND PACKAGING; FLIP CHIP TECHNOLOGIES; LSI CHIPS;

CHIP SCALE PACKAGES;

EID: 51449120936     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMAP.2006.4430593     Document Type: Conference Paper

References (11)

1. e. g., Japan Jisso Technology Roadmap 2003, edited by Japan Electronics & Information Technology Industries Association, Electronic System Integration Technical Committee, and Japan Jisso Technology Roadmap Council, (2003).
2. N. Tanaka, K. Kawano, H. Miura, Y. Kada, and I. Yoshida, "A Highly Reliable Design for a Nonmetallurgical Contact-Joint Structure Consisting of an Adhesive Film," Trans. ASME, J. of Electronic Packaging, Vol. 126, (2004), pp. 82-86.
3. th Electronic Packaging Conference, Singapore, (Dec., 2003), (CD-ROM).
4. A. Hamada, T. Furusawa, N. Saito, and E. Takeda, "A new aspect of mechanical stress effects in scaled MOS devices," IEEE Trans. on Electron Devices, Vol. 38, No. 4 (1991), pp. 895-900.
5. H. Miura and A. Nishimura, "Device Characteristic Changes Caused by Packaging Stress," ASME, Mechanics and Materials for Electronic Packaging, Vol. AMD-195, (1994), pp.101-109.
6. H. Moriya, T. Iwasaki, and H. Miura, 2002, "First Principles Calculation of High Strain-Induced Leakage Current in Silicon Dioxide used for Gate Dielectrics", Ext. Abs. of the 2002 Int. Conf. on Solid State Devices and Materials, pp. 186-187.
7. Y. Kumagai, H. Ohta, H. Miura, and A. Shimizu, "Stress-Optimization of a Thin Film Semiconductor," Proc. of The Int. Symp. On Micro-Mechanical Engineering, Tsuchiura, (Dec., 2003), pp.427-432.
8. C. S. Smith, "Piezoresistance effect in Germanium and Silicon," Physical Review, Vol. 94 (1954), pp. 42-49.
9. D. R Edwards, "Shear stress evaluation of plastic packages," IEEE, Trans. on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-10, No. 4, (1987), pp. 618-627.
10. H. Miura, M. Kitano, A. Nishimura, and S. Kawai, "Thermal stress measurement in silicon chips encapsulated in IC plastic packages," ASME, J. of Electronic Packaging, Vol. 115, (1993), pp. 9-15.
11. J. C. Suhling and R. C. Jaeger, "Silicon Piezoresistive Stress Sensors and Their Application in Electronic Packaging," IEEE, Sensors Journal, Vol. 1, No. 1 (2001), pp. 14-30.