Structural reliability design of plastic packages using Cu-alloy lead-frames

Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003

Volumn , Issue , 2003, Pages 785-790

  Miura, H ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPRESSIVE STRESS; COPPER; DIELECTRIC FILMS; ELECTRONICS PACKAGING; MOLDING; PACKAGING MATERIALS; RESIDUAL STRESSES; RESINS; SILICON; STRESS RELAXATION; STRESSES; THERMAL EXPANSION;

ELECTRONIC PERFORMANCE; MECHANICAL RELIABILITY; METALLIC LEADS; MOLDING RESIN; PLASTIC PACKAGES; STRESS SENSING; STRUCTURAL RELIABILITY; THERMAL EXPANSION COEFFICIENTS;

COPPER ALLOYS;

EID: 84857642656     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1271625     Document Type: Conference Paper

References (10)

1. A. Hamada, T. Furusawa, N. Saito, and E. Takeda, "A new aspect of mechanical stress effects in scaled MOS devices," IEEE Trans. on Electron Devices, Vol. 38, No. 4 (1991), pp. 895-900.
2. D. R Edwards, "Shear stress evaluation of plastic packages," IEEE, Trans. on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-10, No. 4, (1987), pp. 618-627.
3. J. C. Suhling and R. C. Jaeger, "Silicon Piezoresistive Stress Sensors and Their Application in Electronic Packaging," IEEE, Sensors Journal, Vol. 1, No. 1 (2001), pp. 14-30.
4. C. S. Smith, "Piezoresistance effect in Germanium and Silicon," Physical Review, Vol. 94 (1954), pp. 42-49.
5. th Electronic Components and Technology Conf., Las Vegas, NV, May 1990, pp. 316-321.
6. H. Miura, A. Nishimura, S. Kawai, and K. Nishi, "Development and application of the stress-sensing test chip for IC plastic packages," Trans. of the Japan Society of Mechanical Engineers, Vol. 53, No. 493A (1987), pp. 1826-1832.
7. H. Miura, M. Kitano, A. Nishimura, and S. Kawai, "Thermal stress measurement in silicon chips encapsulated in IC plastic packages," ASME, J. of Electronic Packaging, Vol. 115, (1993), pp. 9-15.
8. Y. Kanda, "A graphical representation of the piezoresistance coefficients in silicon, " IEEE Trans. on Electron Devices, Vol. ED-29, No. 1 (1982), pp. 64-70.
9. H. Miura and A. Nishimura, "Device Characteristic Changes Caused by Packaging Stress," ASME, Mechanics and Materials for Electronic Packaging, Vol. AMD-195, (1994), pp.101-109.
10. H. Miura, T. Kumazawa, and A. Nishimura, "Effect of Delamination at Chip/Encapsulant Interface on Chip Stress and Transistor Characteristics," ASME, Application of Experimental Mechanics to Electronic Packaging, Vol. EEP-13, (1995), pp. 73-78.