The viability of 25 Gb/s on-board signalling

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2008, Pages 1121-1127

  Ritter, Mark B ^a   Pepeljugoski, Petar ^a   Gu, Xiaoxiong ^a   Kwark, Young ^a   Kam, Dong ^a   Rimolo Donadio, Renato ^b   Wu, Boping ^c   Baks, Christian ^a   John, Richard ^a   Shan, Lei ^a   Schuster, Christian ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b HAMBURG UNIVERSITY OF TECHNOLOGY   (Germany)

^c UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RATES; ELECTRONIC COMPONENTS;

AGGLOMERATION; COMPUTER NETWORKS; OPTICAL INTERCONNECTS;

SPEED;

EID: 51349147141     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550116     Document Type: Conference Paper

References (15)

1. H. Braunisch, et al, "Flex-Circuit Chip-to-Chip Interconnects", 56th Electronic Components &Technology Conference (2006), p. 1853
2. F.E. Doany, C.L. Schow, L. Schares, C. Baks, R. John, Y-J. Chang, and J.A. Kash, "160-Gb/s Bidirectional Parallel Optical Transceiver Module for Board Level Interconnects using a Single-Chip CMOS IC," Proc. 57th ECTC, pp. 1256-1261, Reno, NV, May/June 2007.
3. Y. Kwark, C. Schuster, L. Shan, C. Baks, J. Trewhella, "The Recessed Probe Launch - A New Signal Launch for High Frequency Characterization of Board Level Packaging", IEC DesignCon Conference, Santa Clara, CA, 2005.
4. S. Rylov, S. Reynolds, D. Storaska, B. Floyd, M. Kapur, T. Zwick, S. Gowda, and M. Sorna, "10+ Gb/s 90-nm CMOS serial link demo in CBGA package," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, Sep. 2005, pp. 1987-1991.
5. J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, W. Rhee, A. V. Rylyakov, H. A. Ainspan, B. D. Parker, M. P. Beakes, A. Chung, T. J. Beukema, P. K. Pepeljugoski, L. Shan, Y. H. Kwark, S. Gowda, and D. J. Friedman, "A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology," IEEE Journal of Solid-State Circuits, vol. 41, no. 12, Dec. 2006, pp. 2885-2900.
6. J. H. Sinsky, A. Adamiecki, and M. Duelk, "10-Gb/s electrical backplane transmission using duobinary signaling," IEEE MTT-S Int,. Microwave Symp. Dig., 2004, pp. 109-112.
7. D. G. Kam, D. R. Stauffer, T. J. Beukema, and M. B. Ritter, "Performance comparison of CEI-25 signaling options and sensitivity analysis," OIF Physical Link Layer (PLL) working group presentation, Nov. 2007.
8. J. Bulzacchelli, T. Beukema, and D. R. Stauffer, "PAM-4 versus NRZ signaling: basic theory," OIF Physical Link Layer (PLL) working group presentation, May 2004.
9. L. Shan, Y. Kwark, P. Pepeljugoski, M. Meghelli, T. Beukema, C. Baks, J. Trewhella, M. Ritter, "Design, analysis and experimental verification of an equalized 10Gbps link," DesignCon 2006.
10. F. Doany et al.: "Measurement of optical dispersion in multimode polymer waveguides", LEOS Summer Topical Meetings, June 2004.
11. Fukatsu, K.; Shiba, K.; Suzuki, Y.; Suzuki, N.; Hatakeyama, H.; Anan, T.; Yashiki, K.; Tsuji, M. "30-Gbps transmission over 100 m-MMFs (GI32) using 1.1 mu m-range VCSELs and receivers," 2007 International Conference on Indium Phosphide and Related Materials : 434-7, Matsue, Japan, 14-18 May 2007
12. W.M.J. Green, M.J. Rooks, L. Sekaric, and Y.A. Vlasov, "Optical modulation using anti-crossing between paired amplitude and phase resonators," Optics Express, v. 15, Issue 25, pp. 17264-17272, Dec. 2007.
13. B. Casper, J. Jaussi, F. O'Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, E. Yeung, and R. Mooney, "A 20 Gb/s Forwarded Clock Transceiver in 90nm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 90-91 Feb. 2006.
14. D. Kam, T. Beukema, Y.H. Kwark, L. Shan, X. Gu, and M.B. Ritter, "Multi-level Signalling in High-density, High-speed Electrical Links," DesignCon 2008.
15. Y.-C. Chang, C.S. Wang, L.A. Coldren, "High-efficiency, high-speed VCSELs with 35 Gbit/s error-free operation"; Electronics LettersVolume 43, Issue 19, September 13 2007 Page(s):1022 -1023