A novel design of CAVLC decoder with low power consideration

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 196-199

  Tsai, Tsung Han ^a   Fang, De Lung ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

MOTION ESTIMATION; MOTION PICTURE EXPERTS GROUP STANDARDS;

MULTI-LEVEL; OPERATION FREQUENCIES; SOLID-STATE CIRCUITS CONFERENCE;

DECODING;

EID: 51349099491     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425764     Document Type: Conference Paper

References (6)

1. ITU-T Rec.H.264/ISO/IEC 11496-10, "Advanced Video Coding", Final Committee Draft, Document JVT-E022, September 2002.
2. H-C Chang, C-C Lin, J-I Guo, "A Novel Low-Cost High-Performance VLSI Architecture for MPEG-4 AVC/H.264 CAVLC Decoding", in Proc. ISCAS'05, pp. 6110-6113, 2005.
3. Wen, Ya-Nan; Wu, Guan-Lin; Chen, Sao-Jie; Hu, Yu-Hen, Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC", APCCAS.2006, 4-7 Dec. 2006 Page(s):1240-1243.
4. Guo-Shiuan Yu, and Tian-Sheuan Chang, "A Zero-Skipping Multi-symbol CAVLC Decoder for MPEG-4 AVC/H.264", ISCAS 2006, 21-24 May 2006.
5. Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, and Jar-Ferr Ynag, "Low Power Design of H.264 CAVLC Decoder", ISCAS 2006, 21-24 May 2006.
6. D. W, G. Wen, M. H., and Z. Ji "A VLSI architecture design of CAVLC decoder", Proc. Intl. Conf. ASIC. pp. 962-965, 2003.