A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI express Gen2 application

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 63-66

  Rhee, Woogeun ^b   Ainspan, Herschel ^a   Friedman, Daniel J ^a   Rasmus, Todd ^c   Garvin, Stacy ^c   Cranford, Clay ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b TSINGHUA UNIVERSITY   (China)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PERIPHERAL EQUIPMENT; INTERFACES (COMPUTER); JITTER; TELECOMMUNICATION SYSTEMS; VARIABLE FREQUENCY OSCILLATORS;

APPLICATIONS.; PCI-EXPRESS; SOLID-STATE CIRCUITS CONFERENCE;

BANDWIDTH;

EID: 51349094675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425732     Document Type: Conference Paper

References (5)

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2. F. Herzel, G. Fischer, and H. Gustat, "An integrated CMOS RF synthesizer for 802.11a wireless LAN," IEEE J. of Solid-State Circuits, vol. 38, pp. 1767-1770, Oct. 2003.
3. A. Loke, et al., "A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking," IEEE J. of Solid-State Circuits, vol. 41, pp. 1894-1907, Aug. 2006.
4. H. Noguchi, T. Tateyama, M. Okamoto, H. Uchida, M. Kimuar, and K. Takashi, "A 9.9G-10.8Gb/s rate-adaptive clock and data recovery with no external reference clock for WDM optical fiber transmission," in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 252-253.
5. B. Soltanian, H. Ainspan, W. Rhee, D. Friedman, and P. Kinget, "An ultra compact differentially tuned 6GHz CMOS LC VCO with dynamic common-mode feedback," in Proc. IEEE CICC, Sep. 2006, pp. 671-674.