Transfer functions for the reference clock jitter in a serial link: Theory and applications

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 1158-1167

  Li, Mike ^a   Martwick, Andy ^b   Talbot, Gerry ^c   Wilstrup, Jan ^d  

^a Wavecrest   (United States)

^b INTEL CORPORATION   (United States)

^c AMD   (United States)

^d TERADYNE INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK DIAGRAMS; CLOCK AND DATA RECOVERY CIRCUITS (CDRC); GIGA BIT ETHERNET (GBE); SERIAL DATA COMMUNICATION ARCHITECTURE;

BIT ERROR RATE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; INPUT OUTPUT PROGRAMS; PHASE LOCKED LOOPS; SCHEMATIC DIAGRAMS; SYNCHRONIZATION; TELECOMMUNICATION LINKS; TRANSFER FUNCTIONS;

JITTER;

EID: 18144407305     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. National Committee for Information Technology Standardization (NCITS), Working Draft for "Fibre Channel -Methodologies for Jitter Specification-MJSQ", Rev 10, 2003.
2. M. Li and J. Wilstrup "Paradigm Shift For Jitter and Noise In Design and Test > 1 Gb/s Communication Systems", ICCD, 2003
3. PCI-SIG, "PCI Express Base Specification, Rev. 1.0a", (www.pcisig.com), 2003
4. W. J. Dally and J. W. Poulton, "Digital Systems Engineering", Cambridge University Press, 1998.
5. A. V. Oppenheim, A. S. Willsky, and S. H. Nawab " Signals & Systems", Prentice Hall, 1996
6. G. E. Carlson "Signals and Linear System Analysis", 2nd edition, John Wiley and Sons, 1998
7. th edition, McGraw Hill, 1999.
8. nd Edition, 1979.