Efficient computation of logic circuits reliability based on probabilistic transfer matrix

International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08

Volumn , Issue , 2008, Pages

  Naviner, Lirida A B ^a   De Vasconcelos, Maí C R ^a   Franco, Denis T ^a   Naviner, Jean François ^a  

^a INSTITUT TELECOM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER NETWORKS; DESIGN; ERROR ANALYSIS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUITS; INTEGRATED CONTROL; MATRIX ALGEBRA; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; NETWORKS (CIRCUITS); PROBABILITY; QUALITY ASSURANCE; RELIABILITY ANALYSIS; SWITCHING CIRCUITS; SWITCHING THEORY; TRANSFER MATRIX METHOD;

DESIGN AND TECHNOLOGY; NANOSCALE ERA; TRANSFER MATRIX;

RELIABILITY;

EID: 51049121623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DTIS.2008.4540217     Document Type: Conference Paper

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