Balancing HPC applications through smart allocation of resources in MT processors

IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM

Volumn , Issue , 2008, Pages

  Boneti, Carlos ^b   Gioiosa, Roberto ^a   Cazorla, Francisco J ^a   Corbalan, Julita ^a,b   Labarta, Jesus ^a,b   Valero, Mateo ^a,b  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; COMPUTER RESOURCE MANAGEMENT; DISTRIBUTED PARAMETER NETWORKS; MECHANISMS; PLANNING; RESOURCE ALLOCATION;

INTERNAL RESOURCES; PARALLEL AND DISTRIBUTED PROCESSING; PERFORMANCE IMPROVEMENTS;

BENCHMARKING;

EID: 51049084882     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2008.4536293     Document Type: Conference Paper

References (34)

1. http://www.top500.org/lists/2007/06.
2. Metis - family of multilevel partitioning algorithms. http://www.cs.umn.edu/ metis.
3. D. Alpert. Will microprocessor become simpler? Microprocessor Report, Nov 2003.
4. E. Ayguade, B. Blainey, A. Duran, J. Labarta, F. Martnez, X. Martorell, and R. Silvera. Is the schedule clause really necessary in openmp? In In Proceedings of the International Workshop of OpenMP Applications and Tools , Lecture Notes in Computer Science. Toronto, Canada., pages 147-159, Jun 2003.
5. D.C. Bossen, J.M. Tendler, and K. Reick. Power4 system design for high reliability. IEEE Micro, 2002.
6. F.J. Cazorla, P.M. W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramirez, and M. Valero. Predictable performance in smt processors: Synergy between the os and smts. IEEE Trans. Comput., 55(7):785-799, 2006.
7. O. Celebioglu, A. Saify, T. Leng, J. Hsieh, V. Mashayekhi, and R. Rooholamini. The performance impact of computational efficiency on HPC clusters with hyper-threading technology. In 18th International Parallel and Dis tributed Processing Symposium (IPDPS'04) - Workshop 14, 2004.
8. M. Curtis-Maury, T. Wang, C. Antonopoulos, and D. Nikolopoulos. Integrating multiple forms of multithreaded execution on multi-smt systems: A study with scientific applications. In Proceedings of the Second International Conference on the Quantitative Evaluation of Systems (QEST'05), pages 199-, 2005.
9. A. Duran, M. Gonzalez, J. Corbalan, X. Martorell, E.Ayguade, J. Labarta, and R. Silvera. Automatic thread distribution for nested parallelism in openmp. In .International Conference on Supercomputing (ICS05).In Proceedings of the 19th ACM International Conference on Supercomputing. Cambridge, Massachusetts, USA, pages 121-130, June 2005.
10. B. Gibbs, B. Atyam, F. Berres, B. Blanchard, L. Castillo, P. Coelho, N. Guerin, L. Liu, C. Diniz Maciel, and C. Thirumalai. Advanced POWER Virtualization on IBM eServer p5 Servers: Architecture and Performance Considerations. IBM Redbook, 2005.
11. R. Gioiosa, F. Petrini, K. Davis, and F. Lebaillif-Delamare. Analysis of System Overhead on Parallel Computers. In The 4th IEEE International Symposium on Signal Processing and Information Technolog y (ISSPIT 2004), Rome, Italy, December 2004. Available from http://bravo.ce.uniroma2.it/home/ gioiosa/pub/isspit04.pdf.
12. W. Huang and D. Tafti. A parallel computing framework for dynamic power balancing in adaptive mesh refinement applications. In Proceedings of Parallel Computational Fluid Dynamics 99.
13. IBM. Cell broadband engine architecture.
14. IBM. Cell broadband engine programming handbook.
15. IBM. PowerPC Architecture book: Book I: User Instruction Set Architecture.
16. IBM. PowerPC Architecture book: Book II: PowerPC Virtual Environment Architecture.
17. IBM. PowerPC Architecture book: Book III: PowerPC Operating Environment Architecture.
18. H. Jin and R.F. Van der Wijngaart. Performance characteristics of the multi-zone nas parallel benchmarks. J. Parallel Distrib. Comput., 66(5):674-685, 2006.
19. R. Kalla, B. Sinharoy, and J.M. Tendler. Ibm power5 chip: A dual-core multithreaded processor. IEEE Micro, 24:40-47, 2004.
20. J. Labarta, S. Girona, V. Pillet, T. Cortes, and L. Gregoris. Dip: A parallel program development environment. In Euro-Par, Vol. II, pages 665-674, 1996.
21. H.Q. Le, W.J. Starke, J.S. Fields, F.P. O'Connell, D.Q. Nguyen, B.J. Ronchetti, W.M. Sauer, E.M. Schwarz, and M. T. Vaden. IBM power6 microarchitecture. IBM Journal of Research and Development, 51:639-662, 2007.
22. D. T. Marr, F. Binns, D.L. Hill, G. Hinton, D.A. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, 6(1), Feb 2002.
23. M. Moreto, F.J. Cazorla, A. Ramirez, and M. Valero. Mlp-aware dynamic cache partitioning. In International Conference on HiPEAC, 2008.
24. NASA. Nas parallel benchmarks. http://www.nas.nasa.gov/Resources/ Software/npb.html.
25. F. Petrini, D. Kerbyson, and S. Pakin. The Case of the Missing Supercomputer Performance: Achieving Optimal Performance on the 8,192 Processors of ASCI Q. In ACM/IEEE SC2003, Phoenix, Arizona, November 10-16, 2003.
26. M.K. Qureshi and Y.N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO, 2006.
27. K. Schloegel, G. Karypis, and V. Kumar. Parallel multilevel algorithms for multi-constraint graph partitioning. Technical report.
28. M.J. Serrano, R. Wood, and M. Nemirovsky. A study of multistreamed superscalar processors. Technical Report #93-05, University of California, Santa Barbara, 1993.
29. Siesta-Project. Siesta: A linear-scaling density-functional method. http://www.uam.es/siesta/.
30. B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Joyner. POWER5 system microarchitecture. IBM Journal of Research and Development, 49(4/5):505-521, 2005.
31. J.M. Soler, E. Artacho, J.D. Gale, A. Garca, J. Junquera, P. Ordejn, and D. Snchez-Portal. The siesta method for ab initio ordern materials simulation. Journal of Physics: Condensed Matter, 14(11), 2002.
32. D. Tsafrir, Y. Etsion, D.G. Feitelson, and S. Kirkpatrick. System noise, os clock ticks, and fine-grained parallel applications. In ICS '05: Proceedings of the 19th annual international conference on Supercomputing, pages 303-312, New York, NY, USA, 2005. ACM Press.
33. D.M. Tullsen, S. Eggers, and H.M. Levy. Simultaneous multi-threading: Maximizing on-chip parallelism. Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 392-403, 1995.
34. C. Walshaw and M. Cross. Dynamic mesh partitioning and load-balancing for parallel computational mechanics codes. 2002.