Chip design of a wave-pipelined PRNG

2006 International Symposium on Communications and Information Technologies, ISCIT

Volumn , Issue , 2006, Pages 978-983

  Sato, Tomoaki ^a   Kikuchi, Kazuhira ^a   Fukase, Masa Aki ^a  

^a HIROSAKI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; COMPUTER NETWORKS; INFORMATION TECHNOLOGY; INTEGRATED CIRCUITS; LOGIC DESIGN; LOGIC DEVICES; NETWORKS (CIRCUITS); NUMBER THEORY; SEQUENTIAL CIRCUITS; SHIFT REGISTERS; SWITCHING CIRCUITS; SWITCHING THEORY; TECHNOLOGY;

INTERNATIONAL SYMPOSIUM; WAVE-PIPELINING;

LOGIC CIRCUITS;

EID: 50949126479     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCIT.2006.339923     Document Type: Conference Paper

References (15)

1. M. Fukase, R. Akaoka, L. Lei, C. T. Shu, and T. Sato, "Hardware Cryptography for Ubiquitous Computing," Proc. of ISCIT2005, vol. 1, pp. 462-465, 2005.
2. M. Fukase, R. Akaoka, and T. Sato, "Hardware Cryptography-Embedded Multimedia Mobile System," Proc. of WMSCI2006, Vol. III, pp. 225-230, Jul. 2006.
3. L. Cotton, "Maximum rate pipelining systems," Procs. AFIPS Spring Joint Computer Conference, pp. 581-586, 1969.
4. F. Klass and M. J. Flynn, "COMPARATIVE STUDIES OF PIPELINED CIRCUITS," Stanford University Technical Report, No. CSL-TR-93-579, July 1993.
5. W. P. Burleson, M. Ciesielski, F. Klass, and W. Liu, "Wave- Pipelining: A Tutorial and Research Survey," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 6, No. 3, pp. 464-474, Sept. 1998.
6. M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "A Wave-Pipelined Biprocessor Achieving Remarkable Compatibility between Low Power and High Speed," Proc. of 10th NASA Symposium on VLSI Design, pp. 8.3.1-8.3.8, Mar. 2002.
7. T. Sato, R. Sakuma, D. Miyamori, and M. Fukase, "High-Speed and Low-Power LFSR by Wave-Pipelining," Proc. of CCCT, Vol. III, pp. 396-401, 2004.
8. D. Miyamori, R. Sakuma, T. Sato, and M. Fukase, "The Evaluation of Wave-Pipelined CRC," 2003 Joint Convention Record, the Hokkaido chapters of the Institutes of Electrical and Information Engineers, pp. 349, 2006.
9. T. Sato, R. Sakuma, D. Miyamori, and M. Fukase, "Hardware Security-Embedded Wireless LAN Processor," Proc. of ECTI-CON 2006, Vol. II, pp. 839-842, 2006.
10. T. Sato, M. Fukase, and T. Nakamura, "Performance analysis of a wave-pipelined ALU," Technical Report of IEICE, CPSY 2000, Vol. 100, No. 20, pp. 1-6, 2000.
11. M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Scaling up of Wave Pipelines," THE FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, Jun. 2000.
12. M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Breakthrough of Superscalar Processors by Multifunctional Wave-Pipelines," Proc. of 9th NASA Symposium on VLSI Design, pp. 6.3.1-6.3.17, Nov. 2000.
13. M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Designing a Wave-Pipelined Vector Processor," Proc. of the Tenth Workshop on Synthesis and System Integration of Mixed Technologies, pp. 351-356, Oct. 2001.
14. Tim Horel and Gary Lauterbach, "UltraSPARC-III: Designing Third-Generation 64-Bit Performance," IEEE Micro, Vol. 19, No. 3, pp. 73-85, 1999.
15. T. Sato, K. Kikuchi, and M. Fukase, "A PRNG Circuit on PLD with Feature of Low-Power, High-Speed, and Various Generation of Random Number Sequence," Proc. of TENCON 2006, 2006 (To be published).