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Volumn , Issue , 2008, Pages 547-550

Challenges in integrating embedded RF within a SOC

Author keywords

Advanced CMOS; Design methodology embedded RF; Isolation; MEMS; RF filters; SIP; SOC

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER NETWORKS; INTEGRATED CIRCUITS;

EID: 50949121548     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RWS.2008.4463550     Document Type: Conference Paper
Times cited : (7)

References (7)
  • 1
    • 33845898791 scopus 로고    scopus 로고
    • GSM /GPRS Single-Chip in 130nm CMOS: Challenges on RF for SoC Integration
    • June
    • D. Seippel, M. Hammes, A. Hanke and J. Kissing, "GSM /GPRS Single-Chip in 130nm CMOS: Challenges on RF for SoC Integration," IEEE RFIC Symposium, June 2006.
    • (2006) IEEE RFIC Symposium
    • Seippel, D.1    Hammes, M.2    Hanke, A.3    Kissing, J.4
  • 4
    • 47349123207 scopus 로고    scopus 로고
    • Substrate Injection Characterization in CMOS Mixed Signal Systems on Chip
    • July
    • L. Rolland du Roscoat, J. Hourany, V. Regnauld, et al., "Substrate Injection Characterization in CMOS Mixed Signal Systems on Chip," IEEE PRIME Conference, July 2007.
    • (2007) IEEE PRIME Conference
    • Rolland du Roscoat, L.1    Hourany, J.2    Regnauld, V.3
  • 5
    • 33847608677 scopus 로고    scopus 로고
    • Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective
    • Feb
    • S. Nuttinck, B. Parvais, G. Curatola, A. Mercha, "Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective," IEEE Transactions on Electron Devices, vol 54 Issue 2, pp. 279-283, Feb. 2007.
    • (2007) IEEE Transactions on Electron Devices , vol.54 , Issue.2 , pp. 279-283
    • Nuttinck, S.1    Parvais, B.2    Curatola, G.3    Mercha, A.4
  • 6
    • 27944462287 scopus 로고    scopus 로고
    • Silicon Based System-in-Package: A passive integration technology combined with advanced packaging and system based design tools to allow a breakthrough in miniaturization
    • Oct
    • F Murray, "Silicon Based System-in-Package: a passive integration technology combined with advanced packaging and system based design tools to allow a breakthrough in miniaturization," IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Oct. 2005.
    • (2005) IEEE Bipolar/BiCMOS Circuits and Technology Meeting
    • Murray, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.