Process models for advanced annealing schemes and their use in device simulation

IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology

Volumn , Issue , 2008, Pages 120-125

  Pichler, P ^a,b   Martinez Limia, A ^a   Kampen, C ^a   Burenkov, A ^a   Schermer, J ^a   Paul, S ^c   Lerch, W ^c   Gelpey, J ^d   McCoy, S ^d   Kheyrandish, H ^e   Pakfar, A ^f   Tavernier, C ^f   Bolze, D ^g  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED SYSTEMS AND DEVICE TECHNOLOGY IISB   (Germany)

^b UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^c MATTSON THERMAL PRODUCTS GMBH   (United States)

^d Mattson Technology Canada Inc   (Canada)

^e CSMA Ltd   (United Kingdom)

^f STMICROELECTRONICS   (France)

^g IHP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; BORON; BORON COMPOUNDS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; RAPID THERMAL ANNEALING; SIMULATED ANNEALING;

ADVANCED ANNEALING; DESIGN AND OPTIMIZATION; DEVICE SIMULATIONS; INDUSTRIAL ENVIRONMENTS; TECHNOLOGY COMPUTER-AIDED DESIGN;

ANNEALING;

EID: 50849091953     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWJT.2008.4540031     Document Type: Conference Paper

References (8)

1. http://www.itrs.net
2. Sentaurus TCAD, Release Y-2006-06, Synopsys, Mountain View, CA, USA
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4. A. Martinez-Limia, P. Pichler, C. Steen, S. Paul, and W. Lerch, Materials Science Forum, 573-574 (2008) 279.
5. N. Zographos, C. Zechner, and I. Avci, Mat. Res. Soc. Symp. Proc., 994 (2007) 0994-F10-01.
6. th IEEE International Conference on Advanced Thermal Processing of Semiconductors RTP 2007 (IEEE, Piscataway, 2007), p. 191.
7. G. Paasch and H. Übensee, phys. stat. sol. (b), 113 (1982) 165.
8. J. Bude, 2000 International Conference on Simulation of Semiconductor Processes and Devices (IEEE, Piscataway, 2000), p. 23.