Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 10, 1999, Pages 1442-1451

  Liu, Le Chin Eugene ^a   Sechen, Carl ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; HEURISTIC METHODS; MICROPROCESSOR CHIPS; TREES (MATHEMATICS);

CHIP-LEVEL GLOBAL ROUTERS; MULTILAYER MACRO-CELL TECHNOLOGY; STEINER TREE HEURISTIC;

ROUTERS;

EID: 0033355612     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.790621     Document Type: Article

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