메뉴 건너뛰기




Volumn 38, Issue 11, 1989, Pages 1604-1608

The Via Minimization Problem is NP-Complete

Author keywords

Layer assignment; layout; NP completeness; printed circuit board; routing; via minimization; VLSI

Indexed keywords

COMPUTER METATHEORY--COMPUTABILITY AND DECIDABILITY;

EID: 0024770040     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.42135     Document Type: Article
Times cited : (34)

References (17)
  • 1
    • 0023089597 scopus 로고
    • Efficient algorithms for layer assignment problem
    • Jan.
    • K. C. Chang and D. H-C. Du, “Efficient algorithms for layer assignment problem,” IEEE Trans. Comput.-Aided Design, vol. CAD-6, no. 1, pp. 67–78, Jan. 1987.
    • (1987) IEEE Trans. Comput.-Aided Design , vol.CAD-6 , Issue.1 , pp. 67-78
    • Chang, K.C.1    Du, D.H-C.2
  • 2
    • 0020751273 scopus 로고
    • A graph-theoretic via minimization algorithm for two-layer printed circuit boards
    • May
    • R-W. Chen, Y. Kajitani, and S-P. Chan, “A graph-theoretic via minimization algorithm for two-layer printed circuit boards,” IEEE Trans. Circuits Syst., vol. CAS-30, no. 5, pp. 284–299, May 1983.
    • (1983) IEEE Trans. Circuits Syst. , vol.CAS-30 , Issue.5 , pp. 284-299
    • Chen, R-W.1    Kajitani, Y.2    Chan, S-P.3
  • 3
    • 0022010454 scopus 로고
    • A linear time algorithm for embedding planar graphs using PQ-trees
    • N. Chiba, T. Nishizeki, S. Abe, and T. Ozawa, “A linear time algorithm for embedding planar graphs using PQ-trees,” J. Comput. Syst. Sci., vol. 30, pp. 54–76, 1985.
    • (1985) J. Comput. Syst. Sci. , vol.30 , pp. 54-76
    • Chiba, N.1    Nishizeki, T.2    Abe, S.3    Ozawa, T.4
  • 4
    • 65849218580 scopus 로고
    • An optimum layer assignment for routing in ICs and PCBs
    • Nashville, TN, June
    • M. J. Cielielski and E. Kinnen, “An optimum layer assignment for routing in ICs and PCBs,” in Proc. 18th Design Automat. Conf., Nashville, TN, June 1981, pp. 733–737.
    • (1981) Proc. 18th Design Automat. Conf. , pp. 733-737
    • Cielielski, M.J.1    Kinnen, E.2
  • 5
    • 0001567493 scopus 로고
    • On straight line representation of planar graphs
    • I. Fary, “On straight line representation of planar graphs,” Acta Sci. Math. (Szeged), vol. 11, pp. 229–233, 1948.
    • (1948) Acta Sci. Math. (Szeged) , vol.11 , pp. 229-233
    • Fary, I.1
  • 6
    • 0000727336 scopus 로고
    • The rectilinear Steiner tree problem is NP-complete
    • June
    • M. R. Garey and D. S. Johnson, “The rectilinear Steiner tree problem is NP-complete,” SIAM J. Appl. Math., vol. 32, no. 4, pp. 826–834, June 1977.
    • (1977) SIAM J. Appl. Math. , vol.32 , Issue.4 , pp. 826-834
    • Garey, M.R.1    Johnson, D.S.2
  • 9
    • 85050951333 scopus 로고
    • Wire routing by optimizing channel assignment within large apertures
    • Atlantic City, NJ, June
    • A. Hashimoto and J. Stevens, “Wire routing by optimizing channel assignment within large apertures,” in Proc. 8th Design Automat. Workshop, Atlantic City, NJ, June 1971, pp. 155–169.
    • (1971) Proc. 8th Design Automat. Workshop , pp. 155-169
    • Hashimoto, A.1    Stevens, J.2
  • 10
    • 0020832099 scopus 로고
    • Minimum via topological routing
    • Oct.
    • C.-P. Hsu, “Minimum via topological routing,” IEEE Trans. Comput.-Aided Design, vol. CAD-2, no. 4, pp. 235–246, Oct. 1983.
    • (1983) IEEE Trans. Comput.-Aided Design , vol.CAD-2 , Issue.4 , pp. 235-246
    • Hsu, C.-P.1
  • 11
    • 0019285289 scopus 로고
    • On via hole minimization of routing on a 2-layer board
    • Oct.
    • Y. Kajitani, “On via hole minimization of routing on a 2-layer board,” in Proc. 1980 IEEE Int. Conf. Circuits Comput., Oct. 1980, pp. 295–298.
    • (1980) Proc. 1980 IEEE Int. Conf. Circuits Comput. , pp. 295-298
    • Kajitani, Y.1
  • 12
    • 0021457417 scopus 로고
    • An unconstrained topological via minimization problem for two-layer routing
    • July
    • M. Marek-Sadowska, “An unconstrained topological via minimization problem for two-layer routing,” IEEE Trans. Comput.-Aided Design, vol. CAD-3, no. 3, pp. 184–190, July 1984.
    • (1984) IEEE Trans. Comput.-Aided Design , vol.CAD-3 , Issue.3 , pp. 184-190
    • Marek-Sadowska, M.1
  • 13
    • 85034630379 scopus 로고
    • On the contact minimization problem
    • Passau, West Germany, Feb.
    • P. Molitor, “On the contact minimization problem,” in Proc. 4th Annu. Symp. Theoret. Aspects Comput. Sci., Passau, West Germany, Feb. 1987, pp. 420–431.
    • (1987) Proc. 4th Annu. Symp. Theoret. Aspects Comput. Sci. , pp. 420-431
    • Molitor, P.1
  • 15
    • 0020291476 scopus 로고
    • Optimal layer assignment for interconnect
    • New York, NY, Sept.
    • R. Y. Pinter, “Optimal layer assignment for interconnect,” in Proc. 1982 IEEE Int. Conf. Circuits Comput., New York, NY, Sept. 1982, pp. 398–401.
    • (1982) Proc. 1982 IEEE Int. Conf. Circuits Comput. , pp. 398-401
    • Pinter, R.Y.1
  • 16
    • 0042477066 scopus 로고
    • Global via elimination in generalized routing environment
    • Tokyo, Japan, June
    • K. R. Stevens and W. M. VanCleemput, “Global via elimination in generalized routing environment,” in Proc. IEEE 1979 Int. Symp. Circuits Syst., Tokyo, Japan, June 1979, pp. 689–692.
    • (1979) Proc. IEEE 1979 Int. Symp. Circuits Syst. , pp. 689-692
    • Stevens, K.R.1    VanCleemput, W.M.2
  • 17
    • 0023366861 scopus 로고
    • On embedding a graph in the grid with the minimum number of bends
    • June
    • R. Tamassia, “On embedding a graph in the grid with the minimum number of bends,” SIAM J. Comput., vol. 16, no. 3, pp. 421–444, June 1987.
    • (1987) SIAM J. Comput. , vol.16 , Issue.3 , pp. 421-444
    • Tamassia, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.