Continuous scaling methodology of planar CMOS transistors by suppressing fluctuation in carrier profile

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 206-207

  Fukutome, Hidenobu ^a   Yoshida, Eiji ^a   Tajima, Mitsugu ^a   Tanaka, Takuji ^a   Sambonsugi, Yasuhiro ^a   Momiyama, Yoichi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; SILICON; SILICON WAFERS; TRANSISTORS;

AMORPHOUS SI; CARRIER PROFILING; CMOS TRANSISTORS; ELECTRICAL FLUCTUATIONS; GATE CAPACITANCE; GATE DEPLETION; GATE STACKS; SCALED CMOS; SCALING METHODOLOGY; VLSI TECHNOLOGIES;

AMORPHOUS SILICON;

EID: 47249084670     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339694     Document Type: Conference Paper

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