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Volumn , Issue , 2007, Pages 75-82

A self-adjusting clock tree architecture to cope with temperature variations

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; DESIGN; INTEGRATED CIRCUITS; PIPELINES; TELECOMMUNICATION NETWORKS; TIME MEASUREMENT; WALLS (STRUCTURAL PARTITIONS);

EID: 50249122050     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397247     Document Type: Conference Paper
Times cited : (16)

References (16)
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    • Within Die Thermal Gradient Impact on Clock Skew: A New Type of Delay-Fault Mechanism
    • Bota, S.A., et al. Within Die Thermal Gradient Impact on Clock Skew: A New Type of Delay-Fault Mechanism, in Int. Test Conf. 2004.
    • (2004) Int. Test Conf
    • Bota, S.A.1
  • 3
    • 46149102947 scopus 로고    scopus 로고
    • Optimal Useful Clock Skew Scheduling in the Presence of Variations Using Robust ILP Formulations
    • Nawale, V., et al. Optimal Useful Clock Skew Scheduling in the Presence of Variations Using Robust ILP Formulations, in Int. Conf. on Computer Aided Design. 2006.
    • (2006) Int. Conf. on Computer Aided Design
    • Nawale, V.1
  • 4
    • 84932133113 scopus 로고    scopus 로고
    • Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming
    • Lee, S., et al. Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming, in Int. Symp. on Low Power Electronics and Design, 2004.
    • (2004) Int. Symp. on Low Power Electronics and Design
    • Lee, S.1
  • 5
    • 0025464163 scopus 로고
    • Clock Skew Optimization
    • Fishburn, J.P., Clock Skew Optimization. IEEE Trans. on Computers, 1990. 39(7): p. 945-951.
    • (1990) IEEE Trans. on Computers , vol.39 , Issue.7 , pp. 945-951
    • Fishburn, J.P.1
  • 6
    • 0028571323 scopus 로고
    • A Graph-Theoretic Approach to Clock Skew Optimization
    • Deoka, R.B., et al. A Graph-Theoretic Approach to Clock Skew Optimization, in Int. Symp. on Circuits and Systems, 1994.
    • (1994) Int. Symp. on Circuits and Systems
    • Deoka, R.B.1
  • 7
    • 33747530935 scopus 로고    scopus 로고
    • Clock Distribution Networks in Synchronous Digital Integrated Circuits
    • Friedman, E.G., Clock Distribution Networks in Synchronous Digital Integrated Circuits. Proc. of the IEEE, 2001.89(5): p. 665-692.
    • (2001) Proc. of the IEEE , vol.89 , Issue.5 , pp. 665-692
    • Friedman, E.G.1
  • 8
    • 0025415048 scopus 로고
    • Alpha-Power Law MOSFET Model and Its Application to CMOS Inverter Delay and Other Formulas
    • Sakurai, T., et al., Alpha-Power Law MOSFET Model and Its Application to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid-State Circuits, 1990. 25: p. 584-593.
    • (1990) IEEE Journal of Solid-State Circuits , vol.25 , pp. 584-593
    • Sakurai, T.1
  • 10
    • 0033712799 scopus 로고    scopus 로고
    • New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design
    • Cao, Y., et al. New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design. in Custom Integrated Circuit Conf. 2000.
    • (2000) Custom Integrated Circuit Conf
    • Cao, Y.1
  • 11
    • 0025433816 scopus 로고
    • Systolic Evaluation of Polynomial Expressions
    • Mathias, P.C., et al., Systolic Evaluation of Polynomial Expressions. IEEE Trans. on Computers, 1990. 39(5): p. 653-665.
    • (1990) IEEE Trans. on Computers , vol.39 , Issue.5 , pp. 653-665
    • Mathias, P.C.1
  • 13
    • 0029230250 scopus 로고
    • A Design of Reed-Solomon Decoder with Systolic-Array Structure
    • Iwamura, K., et al., A Design of Reed-Solomon Decoder with Systolic-Array Structure. IEEE Trans. on Computers, 1995. 44(1): p. 118-122.
    • (1995) IEEE Trans. on Computers , vol.44 , Issue.1 , pp. 118-122
    • Iwamura, K.1
  • 14
    • 0035394088 scopus 로고    scopus 로고
    • Compensation of Mobility and Threshold Voltage Temperature Effects with Application in CMOS Circuits
    • 48
    • Filanovsky, I.M., et al., Compensation of Mobility and Threshold Voltage Temperature Effects with Application in CMOS Circuits. IEEE Trans. on Circuit and Systems 1, 2001. 48(7): p. 876-884.
    • (2001) IEEE Trans. on Circuit and Systems , vol.1 , Issue.7 , pp. 876-884
    • Filanovsky, I.M.1
  • 16
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    • A Polynomial Combinatorial Algorithm for Generalized Minimum Cost Flow
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.