Within die thermal gradient impact on clock-skew: A new type of delay-fault mechanism

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 1276-1284

  Bota, S A ^a   Rosales, M ^a   Rosello J L ^a   Keshavarzi, A ^a,b   Segura, J ^a  

^a UNIVERSITAT DE LES ILLES BALEARS   (Spain)

^b INTEL CORPORATION   (United States)

Author keywords

Clock distribution networks; Clock skew; Interconnect delay; Temperature gradient

Indexed keywords

ALGORITHMS; DIES; ELECTRIC FAULT CURRENTS; ELECTRIC POTENTIAL; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; ROUTERS; SPURIOUS SIGNAL NOISE; THERMAL EFFECTS; THERMAL GRADIENTS; VLSI CIRCUITS;

CLOCK DISTRIBUTION NETWORKS; CLOCK SKEW; INTERCONNECT DELAY; TEMPERATURE GRADIENTS;

ELECTRIC CLOCKS;

EID: 18144362903     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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