A novel low leakage-current Ni SALICIDE process in nMOSFETs on Si(110) substrate

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 139-142

  Yamaguchi, T ^a   Kashihara, K ^a   Kudo, S ^a   Hayashi, K ^a   Hashikawa, N ^a   Okudaira, T ^a   Tsutsumi, T ^a   Maekawa, K ^a   Oda, H ^a   Asai, K ^a   Kojima, M ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; NICKEL; NICKEL ALLOYS; SILICON;

LOW LEAKAGE; N-MOSFETS; OFF-STATE LEAKAGE; SALICIDE; SI(110);

ELECTRIC BREAKDOWN;

EID: 50249119672     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418884     Document Type: Conference Paper

References (6)

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4. T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, and S. Takagi, "(110)-surface straind-SOI CMOS devices with higher carrier mobility," Symp. on VLSI Tech. Dig., pp.97-98, 2003
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6. T. Yamaguchi et al., "Suppression ofanomalous gate edge leakage current by control of Ni silicidation region using Si ion implantation technique," IEDMTech. Dig., pp.855-858, 2006