Novel anisotropie strain engineering on (110)-surface SOI CMOS devices using combination of local/global strain techniques

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Mizuno, T ^a,b   Irisawa, T ^a   Hirashita, N ^a   Moriyama, Y ^a   Numata, T ^a   Tezuka, T ^a   Sugiyama, N ^a   Takagi, S ^a,c  

^a TOSHIBA CORPORATION   (Japan)

^b KANAGAWA UNIVERSITY   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; ELECTRON DEVICES; MOSFET DEVICES; TECHNOLOGY;

RELAXATION EFFECTS; SGOI SUBSTRATES; SIGE LAYERS; SOI CMOS; STRAIN ENGINEERING; STRAINED-SOI;

SURFACE RELAXATION;

EID: 46049117355     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346810     Document Type: Conference Paper

References (4)

1. T.Mizuno el al., IEEE Trans. Electron Devices, ED-52, 367, 2005.
2. T. Irisawa et al., VLSI Symp. Tech. Dig., p. 178, 2005.
3. H. Irie et al., IEDM Tech. Dig., p.225, 2004.
4. M. Fischetti et al., MRS Spring Meeting, 2006.