Temperature aware microprocessor floorplanning considering application dependent power load

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 586-589

  Chu, N Ta ^a   Zhang, Xinyi ^a   He, Lei ^a   Jing, Tom Tong ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; COMPUTER-AIDED DESIGN; CYCLES PER INSTRUCTION; FLOOR-PLANNING; HEAT DIFFUSIONS; HOT SPOTTING; INTERCONNECT PIPELINING; INTERNATIONAL CONFERENCES; ON CHIPS; PEAK TEMPERATURES; POWER LOADS; THERMAL ANALYSIS; THROUGHPUT OPTIMIZATION;

DESIGN; ELECTRIC LOAD FORECASTING; SEMICONDUCTOR DOPING; THERMOANALYSIS;

STOCHASTIC MODELS;

EID: 50249105864     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397328     Document Type: Conference Paper

References (12)

1. M. Ekpanyapong, J. R. Minz, T. Watewai, H. S. Lee, and S. K. Lim, "Profile-guided microarchitecture floorplanning for deep submicro processor design," in IEEE/ACM Design Automation Conf., 2004.
2. C. Long, L. Simonson, W. Liao, and L. He, ''Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects," in IEEE/ACM Design Automation Conf., 2004.
3. A. Jagannathan, H. H. Yang, K. Konigsfeld, D. Milliron, M. Mohan, M. Romesis1, G. Reinman, and J. Cong1, "Microarchitecture evaluation with floorplanning and interconnect pipelining," in Asia South Pacific Design Automation Conf., pp. 1-8 2004.
4. K. Sankaranarayanan, S. Velusamy, M. R. Stan, and K. Skadron, "A case for thermal-aware floorplanning at the microarchitectural level," in Journal of Instruction-Level Parallelism, 2005.
5. K. Skadrona, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan, "Temperature-aware microarchitecture," in Proc. IEEE Int. Symp. on Circuits and Systems, 2003.
6. V. Nookala, D. J. Lilja, and S. S. Sapatnekar, "Temperature-aware floorplanning of microarchitecture blocks with ipc-power dependence modeling and transient analysis," in Int. Symp. on Low Power Electronics and Design, 2006.
7. Y. Han, I. Koren, and C. A. Moritz, "Temperature aware floorplanning," in Temperature aware. Computing Systems, 2005.
8. Technical Report EE of UCLA, 2007, http://eda.ee.ucla.edu.
9. N. Sherwani, "Algorithms for vlsi design automation," Kluwer, 3rd ed., 1999.
10. S. N. Adya and I. L. Markov, "Fixed-outlined floorplanning through better local research," in IEEE/ACM Int. Conf. on Computer Aided Design, pp. 328-334, 2001.
11. W. Liao, L. He, and K. Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1042-1053, 2005.
12. J. L. Henning, "SPEC CPU 2000:Measuring CPU performance in the new millennium," IEEE Trans. on Computers, pp. 28-35 vol.33, 2000.