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Volumn , Issue , 2006, Pages 622-626
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Reliability improvement of 90nm large flip chip low-k die via dicing and assembly process optimization
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Author keywords
[No Author keywords available]
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Indexed keywords
ASSEMBLY PROCESSING;
CHEMICAL-;
DIAMOND BLADES;
DIE SIZE;
ELECTRICAL PERFORMANCES;
ENHANCED DIELECTRIC PROPERTIES;
FIELD PROGRAMMABLE GATE ARRAY;
FLIP CHIP DIES;
FLIP CHIP RELIABILITY;
FLIP CHIPPING;
LASER DICING;
LASER GROOVING;
LOGIC CELLS;
LOW-K DIELECTRIC MATERIALS;
LOW-K MATERIALS;
MECHANICAL DICING;
PACKAGING TECHNOLOGIES;
POOR ADHESION;
PROCESS WINDOWS;
PROCESSING SPEEDS;
RELIABILITY IMPROVEMENT;
SIGNAL ROUTING;
SILICON TECHNOLOGIES;
SINGULATION;
UNDERFILL;
ADHESION;
CHEMICAL PROPERTIES;
CHIP SCALE PACKAGES;
DIAMONDS;
DIELECTRIC PROPERTIES;
DIES;
ELECTRIC CURRENTS;
ELECTRONIC EQUIPMENT MANUFACTURE;
ELECTRONICS PACKAGING;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
FLIP CHIP DEVICES;
LASERS;
LITHOGRAPHY;
LOGIC DEVICES;
MATERIALS PROPERTIES;
MATERIALS SCIENCE;
MECHANICAL PROPERTIES;
NONMETALS;
OPTIMIZATION;
QUALITY ASSURANCE;
RELIABILITY;
RELIABILITY ANALYSIS;
SILICON;
SILICON WAFERS;
SPEED;
STRESSES;
TECHNOLOGY;
THERMAL EXPANSION;
THERMAL SPRAYING;
DIELECTRIC MATERIALS;
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EID: 50249085545
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/EPTC.2006.342785 Document Type: Conference Paper |
Times cited : (8)
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References (3)
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