Novel ZrO2/Si3N4 dual charge storage layer to form step-up potential wells for highly reliable multi-level cell application

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 83-86

  Zhang, Gang ^a   Wan, Sik Hwang ^b   Bobade, Santosh M ^a   Lee, Seung Hwan ^a   Cho, Byung Jin ^b   Won, Jong Yoo ^a  

^a Sungkyunkwan University   (South Korea)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES;

ZIRCONIUM ALLOYS;

EID: 50249084540     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418869     Document Type: Conference Paper

References (11)

1. C. Friederich et. al., "Multi-level p+ tri-gate SONOS NAND string arrays," IEDM 2006, p.963.
2. S. Kim et. al., "Robust Multi-bit Programmable Flash Memory Using a Resonant Tunnel Barrier," IEDM 2005, p.881.
3. B. Eitan et. al., "4-bit per Cell NROM Reliability," IEDM 2005, p.547.
4. M.-H. Chi et. al., "Multi-level Flash/EPROM Memories: New Self-convergent Programming Methods for Low-voltage Applications," IEDM 1995, p.271.
5. S.-J. Shen et. al., "Novel Self-Convergent Programming Scheme for Multi-Level P-channel Flash Memory," IEDM 1997, p.287.
6. P. Candelier et. al., "Hot Carrier Self Convergent Programming Method for Multi-Level Flash Cell Memory," IRPS 1997, p.104.
7. M. She et. al., "Silicon-Nitride as a Tunnel Dielectric for Improved SONOS-Type Flash Memory," EDL v24n5, p.309, 2003.
8. Y.N. Tan et. al., "Over-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer," T-ED v51n7, p.1143, 2004.
9. Y. Kamakura et. al., "Investigation of Hot-Carrier-Induced Breakdown of Thin Oxide," IEDM 1997, p.81.
10. C.C. Yeh et. al., "A novel NAND-type PHINES nitride trapping storage flash memory cell with physically 2-bits-per-cell storage, and a high programming throughput for mass storage applications," VLSI. Tech. 2005, p.116.
11. H.-T. Lue et. al., "A Transient Analysis Method to Characterize the Trap Vertical Location in Nitride-Trapping Devices," EDL v25nl2, p.816, 2004.