SCOPUS 정보 검색 플랫폼

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2006, Pages 273-276

High-speed flex chip-to-chip interconnect

(3) Braunisch, Henning a Jaussi, James E a Mix, Jason A a

a INTEL CORPORATION (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; NETWORKS (CIRCUITS);

20 GB/S; CHIP-TO-CHIP INTERCONNECTS; CMOS CIRCUITS; ELECTRICAL PERFORMANCES; ELECTRONIC PACKAGING; HIGH FREQUENCY PERFORMANCE; HIGH SPEEDS; SIGNALING RATES;

CHIP SCALE PACKAGES;

EID: 50049109580 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/EPEP.2006.321153 Document Type: Conference Paper

Times cited : (4)

References (5)

1
- 33845567938
- Flex-circuit chip-to-chip interconnects
- San Diego, CA, May 30-June 2
- H. Braunisch, J. E. Jaussi, J. A. Mix, M. B. Trobough, B. D. Horine, V. Prokofiev, D. Lu, R. Baskaran, P. C. H. Meier, D.-H. Han, K. E. Mallory, and M. W. Leddige, "Flex-circuit chip-to-chip interconnects," in Proc. IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 30-June 2, 2006, pp. 1853-1859.
- (2006) Proc. IEEE Electronic Components and Technology Conf. (ECTC) , pp. 1853-1859
- Braunisch, H.¹ Jaussi, J.E.² Mix, J.A.³ Trobough, M.B.⁴ Horine, B.D.⁵ Prokofiev, V.⁶ Lu, D.⁷ Baskaran, R.⁸ Meier, P.C.H.⁹ Han, D.-H.¹⁰ Mallory, K.E.¹¹ Leddige, M.W.¹²

2
- 11944257220
- 8 Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew
- Jan
- J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. Casper, A. Marlin, J. Kennedy, N. Shanbhag, and R. Mooney, "8 Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew," IEEE J. Solid-State Circuits, vol. 40, pp. 80-88, Jan. 2005.
- (2005) IEEE J. Solid-State Circuits , vol.40 , pp. 80-88
- Jaussi, J.E.¹ Balamurugan, G.² Johnson, D.R.³ Casper, B.⁴ Marlin, A.⁵ Kennedy, J.⁶ Shanbhag, N.⁷ Mooney, R.⁸

3
- 35348832086
- A 20 Gb/s forwarded clock transceiver in 90 nm CMOS
- San Francisco, CA, Feb. 5-9
- B. Casper, J. Jaussi, F. O'Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, E. Yeung, and R. Mooney, "A 20 Gb/s forwarded clock transceiver in 90 nm CMOS," in Digest IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 5-9, 2006, pp. 90-91, 640.
- (2006) Digest IEEE Int. Solid-State Circuits Conf. (ISSCC)
- Casper, B.¹ Jaussi, J.² O'Mahony, F.³ Mansuri, M.⁴ Canagasaby, K.⁵ Kennedy, J.⁶ Yeung, E.⁷ Mooney, R.⁸

4
- 39049092602
- A 20 Gb/s embedded clock transceiver in 90 nm CMOS
- San Francisco, CA, Feb. 5-9
- J. Jaussi, B. Casper, M. Mansuri, F. O'Mahony, K. Canagasaby, J. Kennedy, and R. Mooney, "A 20 Gb/s embedded clock transceiver in 90 nm CMOS," in Digest IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 5-9, 2006, pp. 340-341, 657.
- (2006) Digest IEEE Int. Solid-State Circuits Conf. (ISSCC)
- Jaussi, J.¹ Casper, B.² Mansuri, M.³ O'Mahony, F.⁴ Canagasaby, K.⁵ Kennedy, J.⁶ Mooney, R.⁷

5
- 10444239308
- Compliant die-package interconnects at high frequencies
- Las Vegas, NV, June 1-4
- H. Braunisch, K.-P. Hwang, and R. D. Emery, "Compliant die-package interconnects at high frequencies," in Proc. IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, June 1-4, 2004, pp. 1237-1243.
- (2004) Proc. IEEE Electronic Components and Technology Conf. (ECTC) , pp. 1237-1243
- Braunisch, H.¹ Hwang, K.-P.² Emery, R.D.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.