Compilation strategies for reducing code size on a VLIW processor with variable length instructions

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4917 LNCS, Issue , 2008, Pages 147-160

  Hahn, Todd T ^a   Stotzer, Eric ^a   Sule, Dineel ^a   Asal, Mike ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODE SIZE; DSP PROCESSORS; EMBEDDED ARCHITECTURES; INSTRUCTION SET EXTENSIONS; INTERNATIONAL CONFERENCES; NO REDUCTION; OBJECT CODING; PERFORMANCE TRADE OFFS; REDUCED CODE; VARIABLE LENGTHS;

CODES (STANDARDS); CODES (SYMBOLS); DIGITAL SIGNAL PROCESSING; ELECTRIC POWER UTILIZATION; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; VERY LONG INSTRUCTION WORD ARCHITECTURE;

PROGRAM COMPILERS;

EID: 49949109181     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77560-7_11     Document Type: Conference Paper

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