Hardware architecture to realize multi-layer image processing in real-time

IECON Proceedings (Industrial Electronics Conference)

Volumn , Issue , 2007, Pages 2478-2483

  Lu, Chieh Lun ^a   Fu, Li Chen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNUAL CONFERENCE; COMPUTING SYSTEMS; DATA FLOWS; HARDWARE ARCHITECTURE; HARDWARE DESIGNS; HARRIS-CORNER DETECTORS; IMAGE ALGORITHMS; MULTI LAYERING; MULTI SCALING; PARALLEL AND PIPELINE; ROBOTIC APPLICATIONS; RUNNING-IN; TIME CONSUMING; TIMING DELAYS; VISUAL DATA;

CHLORINE COMPOUNDS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SYSTEMS; DATA PROCESSING; DATA STORAGE EQUIPMENT; DIGITAL COMPUTERS; DIGITAL IMAGE STORAGE; ELECTRONICS INDUSTRY; IMAGE PROCESSING; IMAGING SYSTEMS; IMAGING TECHNIQUES; INDUSTRIAL ELECTRONICS; OPTICAL DATA PROCESSING; PIPELINES; PROCESS ENGINEERING;

HARDWARE;

EID: 49949095899     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2007.4460387     Document Type: Conference Paper

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