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1
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31344455697
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Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering
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Jan
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B. Calhoun, and A. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering," IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp. 238-245, Jan. 2006.
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(2006)
IEEE Journal of Solid-State Circuits
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, Issue.1
, pp. 238-245
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Calhoun, B.1
Chandrakasan, A.2
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2
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39749186100
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Performance and variability optimization strategies in a sub-200mV, 3.5pJ/inst, 11nW subthreshold processor
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June
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S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhan-dali, T. Austin, D. Sylvester, and D. Blaauw, "Performance and variability optimization strategies in a sub-200mV, 3.5pJ/inst, 11nW subthreshold processor," IEEE Symposium on VLSI Circuits, pp. 152-153, June 2007.
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(2007)
IEEE Symposium on VLSI Circuits
, pp. 152-153
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Hanson, S.1
Zhai, B.2
Seok, M.3
Cline, B.4
Zhou, K.5
Singhal, M.6
Minuth, M.7
Olson, J.8
Nazhan-dali, L.9
Austin, T.10
Sylvester, D.11
Blaauw, D.12
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3
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37749015480
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A 85mV 40nW process-tolerant subthreshold 8×8 FIR filter in 130nm technology
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June
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M. Hwang, A. Raychowdhury, K. Kim, and K. Roy, "A 85mV 40nW process-tolerant subthreshold 8×8 FIR filter in 130nm technology," IEEE Symposium on VLSI Circuits, pp. 154-155, June 2007.
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(2007)
IEEE Symposium on VLSI Circuits
, pp. 154-155
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Hwang, M.1
Raychowdhury, A.2
Kim, K.3
Roy, K.4
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4
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33847144137
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Challenge: Variability characterization and modeling for 65- to 90-nm processes
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Sep
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H. Masuda, S. Ohkawa, A. Kurokawa and M. Aoki, "Challenge: variability characterization and modeling for 65- to 90-nm processes," IEEE Custom Integrated Circuits Conference, pp. 593-600, Sep. 2005.
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(2005)
IEEE Custom Integrated Circuits Conference
, pp. 593-600
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Masuda, H.1
Ohkawa, S.2
Kurokawa, A.3
Aoki, M.4
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5
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49749123368
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A wide range spatial frequency analysis of intra-die variations with 4-mm 4000 × 1 transistor arrays in 90nm CMOS
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Sep
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D. Levacq, T. Minakawa, M. Takamiya, and T. Sakurai, "A wide range spatial frequency analysis of intra-die variations with 4-mm 4000 × 1 transistor arrays in 90nm CMOS," IEEE Custom Integrated Circuits Conference, pp. 257-260, Sep. 2007.
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(2007)
IEEE Custom Integrated Circuits Conference
, pp. 257-260
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Levacq, D.1
Minakawa, T.2
Takamiya, M.3
Sakurai, T.4
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6
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0036858210
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Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
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Nov
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J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1396-1402, Nov. 2002.
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(2002)
IEEE Journal of Solid-State Circuits
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, Issue.11
, pp. 1396-1402
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Tschanz, J.1
Kao, J.2
Narendra, S.3
Nair, R.4
Antoniadis, D.5
Chandrakasan, A.6
De, V.7
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