Built-in Duty Cycle Corrector using Coded Phase Blending Scheme for DDR/DDR2 Synchronous DRAM Application

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 287-288

  Kim, Kyu Hyoun ^a   Cho, Geun Hee ^a   Lee, Jung Bae ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

DCC; DLL; Phase blending and DDR SDRAM

Indexed keywords

BANDWIDTH; JITTER; MICROPROCESSOR CHIPS;

DUTY CYCLE CORRECTION (DCC);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0141426665     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. B. Lee, K-h. Kim et al., " Digitally controlled DLL and I/O circuits for 500Mb/s/pin × 16 DDR SDRAM," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 68-69.
2. B. W. Garlepp et al., "A portable digital DLL for high-speed CMOS interface circuits," IEEEJ. Solid-State Circuits, vol. 34, pp. 632-644, May. 1999.
3. K. Nakamura, M. Fukaishi, Y. Hirota, Y Nakazawa and M. Yotsuyanagi, "A CMOS 50% duty cycle repeater using complementary phase blending," in Symp. VLSI Circuits Dig. Tech. Papers, pp. 48-49, Jun. 2000.
4. W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University press, 1998, pp. 639-641