DC bias effects on data retention at room temperature in SONOS nonvolatile memory devies

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2007, Pages 147-149

  Hwang, Jeong Mo ^a   Wallinger, Todd ^a  

^a Simtek Corp   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECAY (ORGANIC); EXPONENTIAL FUNCTIONS; SILICON NITRIDE; SILICON OXIDES; SILICON WAFERS; THRESHOLD VOLTAGE;

CHARGE LOSS; DATA-RETENTION; DC BIAS; DC BIAS EFFECT; GATE BIAS; NEGATIVE BIAS; PROGRAM STATE; SILICON NON-VOLATILE MEMORY; SILICON OXIDE NITRIDE OXIDE SILICONS; SILICON TRANSISTORS;

ROOM TEMPERATURE;

EID: 49549100216     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2007.4469243     Document Type: Conference Paper

References (9)

1. K. Kim, and J. Choi, "Future Outlook of NAND Flash Technology for 40nm Node and Beyond," in Proc. IEEE NVSM Workshop, 2006, pp.9-11
2. B. De Salvo, et al., "Performance and Reliability Features of Advanced Non-volatile Memories Based on Discrete Traps (Silicon Nanocrystals and SONOS) , " IEEE Trans. Device and Materials Reliability, vol.4, pp.377-389, September 2004
3. M.H. White, D.A. Adams, and J. Bu, "On the Go with SONOS," IEEE Circuits and Devices, vol. 16, pp. 22-31, May 2000
4. T.H. Kim, et al., "Charge decay characteristics of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures and extraction of the nitride trap density distribution," Appl. Physics Lett., vol 85, pp.660-662, Jul. 2004
5. Y. Wang, and M.H. White, "An analytical retention model for SONOS non-volatile memory devices in the excess electron state," Solid State Electronics, vol.49, pp.97-107, 2005
6. C. E. Herdt, et al., "Non-Volatile RAM with Integrated Compact Static RAM Load Configuration," U.S. Patent 5065362, Nov. 12, 1991
7. R. van Schaijk, et al., " Reliability of embedded SONOS memories, " in Proc. ESSDERC, 2004, pp.277-280
8. S. Kumar, and E. Russel, "Model to Predict Reliability of ONO Non-Volatile Memory," in IEEE International Integrated Reliability Workshop (IIRW), 2001, pp.34-40
9. N. Akil, et al., "Depletion 2-Transistor-SONOS Flash memories with zero gate voltage read out," in Proc. ICMTD-2007, pp.201204