The search for alternative computational paradigms

IEEE Design and Test of Computers

Volumn 25, Issue 4, 2008, Pages 334-343

  Shanbhag, Naresh R ^a   Mitra, Subhasish ^b   de Veciana, Gustavode ^c   Orshansky, Michael ^c   Marculescu, Radu ^d   Roychowdhury, Jaijeet ^e   Jones, Douglas ^a   Rabaey, Jan M ^f  

^a United States of America   (United States)

^b STANFORD UNIVERSITY   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^d CARNEGIE MELLON UNIVERSITY   (United States)

^e UNIVERSITY OF MINNESOTA   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

CNT; Computational efficiency; Computational modeling; Computing; Couplings; Energy efficiency; Logic; Low power; Models; Nanometers; Nanoscale; Networks; Oscillators; Robust; Robustness

Indexed keywords

CARBON NANOTUBES; CONSERVATION; COST EFFECTIVENESS; EFFICIENCY; ERROR CORRECTION; FABRICS; INDUSTRIAL ENGINEERING; NANOTECHNOLOGY; NONMETALS; SILICON;

CARBON NANOTUBES (CNTS); CNT; COMPUTATIONAL EFFICIENCY; COMPUTATIONAL MODELING; COMPUTATIONAL PARADIGMS; COMPUTATIONAL SYSTEMS; COMPUTING; COUPLINGS; DENSE NETWORKS; DESIGNING ROBUST; ENERGY EFFICIENCY PROBLEM; FABRIC DESIGNS; INFORMATION EXCHANGING; LOGIC; LOW POWER; LOW POWERS; MODELS; MODELS OF COMPUTATION; NANO SCALING; NANOMETERS; NANOSCALE; NETWORKS; NEW MODES; NON-IDEALITIES; OSCILLATORS; PROCESS TECHNOLOGIES; PROCESS VARIATIONS; ROBUST; ROBUSTNESS; SILICON DEVICES; SOFT ERRORS; STATISTICAL VARIATIONS;

ENERGY EFFICIENCY;

EID: 49549083029     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2008.113     Document Type: Article

References (12)

1. International Technology Roadmap for Semiconductors, http:// www.itrs.net/Links/2006Update/2006UpdateFinal. htm.
2. J. Deng et al., "Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections," Proc. Int'l. Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 570-588.
3. J. Von Neumann, "Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components," Automata Studies, C.E. Shannon, and J. McCarthy, Eds. Princeton Univ. Press, 1956, pp. 43-98.
4. E.F. Moore and C.E. Shannon, "Reliable Circuits Using Less Reliable Relays," J. Franklin Institute, vol. 262, Sept. 1956, pp. 191-208, 281-297.
5. N.R. Shanbhag, "A Mathematical Basis for Power-Reduction in Digital VLSI Systems," IEEE Trans. Circuits and Systems, part II, vol. 44, no. 11, Nov. 1997, pp. 935-951.
6. A.J. Koch and H. Meinhardt, "Biological Pattern Formation: From Basic Mechanisms to Complex Structures," Reviews of Modern Physics, vol. 66, no. 4, Oct. 1994, pp. 1481-1507.
7. G. Varatkar et al., "Sensor Network-on-Chip," Proc. IEEE Int'l Symp. System-on-Chip, IEEE Press, 2007.
8. P. Huber, Robust Statistics, John Wiley & Sons, 1981.
9. W. Maass, T. Natschlager, and H. Markram, "Real-Time Computing without Stable States: A New Framework for Neural Computation Based on Perturbations," Neural Computation, vol. 14, no. 11, Nov. 2002, pp. 2531-2560
10. P. Bogdan, T. Dumitras, and R. Marculescu, "Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip," VLSI Design, vol. 2007, article 95348 (17 pp.).
11. N. Patil et al., "Automated Design of Misaligned-Carbon Nanotube-Immune Circuits," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 958-961.
12. A.K. Singh et al., "A Heterogeneous CMOS-CNT Architecture Utilizing Novel Coding of Boolean Functions," Proc. IEEE Int'l Symp. Nanoscale Architectures, IEEE Press, 2007, pp. 15-20.