Stacked BSCR ESD protection for 250V tolerant circuits

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn 16, Issue , 2004, Pages 225-228

  Vashchenko, V A ^a   Concannon, A ^a   Ter Beek, M ^a   Hopper, P ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; POLYSILICON;

BJT PROCESS; CLAMPING VOLTAGE; ESD PROTECTION; TOLERANT CIRCUIT;

ELECTRIC NETWORK ANALYSIS;

EID: 4944258343     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/wct.2004.239937     Document Type: Conference Paper

References (7)

1. J. Z. Chen, A. Amerasekera, T. Vrotsos, "Bipolar SCR ESD protection circuit for high speed subnricion bipolar/BiCMOS circuits" IEDM 1995, p 337-340.
2. V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "Comparison of ESD Protection Capability of lateral BJT, SCR and bidirectional SCR for Hi-Voltage BiCMOS Circuits", in Proceed, of BCTM, 2002, pp.181-184.
3. V.A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "High performance SCR's for on-chip ESD Protection in High Voltage BCD Processes" Proceed ISPSD 2003 pp.261-264.
4. S. Joshi, R. Ida, and E. Rosenbaum "A study of vertical SiGe thyristor design and optimization," in Proceedings of the ESD/EOS Symposium 2003, pp. 224-232.
5. V. A. Vashchenko, W.Kindt, M. ter Beek, and P. Hopper "Implementation of 60V Tolerant Dual Direction ESD Protection in 5V BiCMOS Process for Automotive Application", in print Proceed of ESD/EOS Symp., 2004, in print
6. V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "Bipolar SCR ESD Protection in a 0.25 μm Si-Ge Process Using Sub-Collector Region Modification", in print Proceed. IRPS. 2004, paper 8B4. in print
7. "TSUPREME4", "MEDICI", Versions 2003.12.0. Reference Manual, Synopsys, 2003.