IC cost reduction by applying embedded fault tolerance for Soft Errors

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 20, Issue 5 SPEC.ISS., 2004, Pages 533-542

  Nieuwland, André K ^a   Kleihorst, Richard P ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

BISR; Defect density; Fault tolerant; IC cost; IC production; On line test; Redundancy; SER; SEU; Soft error; Yield

Indexed keywords

COMPUTATIONAL COMPLEXITY; COSTS; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; REDUNDANCY; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SENSITIVITY ANALYSIS; SPECIFICATIONS;

BUILT IN SELF REPAIR (BISR); DEFECT DENSITY; IC COST; IC PRODUCTION; ON-LINE TEST; SER; SINGLE EVENT UPSETS (SEU); SOFT ERROR; YIELD;

INTEGRATED CIRCUITS;

EID: 4944258212     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:JETT.0000042517.30698.ad     Document Type: Conference Paper

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