Digital current mode control architecture with improved performance for dc-dc converters

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn , Issue , 2008, Pages 1087-1092

  Li, Jian ^a   Lee, Fred C ^a  

^a Virginia Polytechnic Institute and State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; DC-DC CONVERTERS; DIGITAL ARITHMETIC; DIGITAL CONTROL SYSTEMS; ENERGY CONSERVATION; EXHIBITIONS;

CURRENT MODE CONTROLLED; DESIGN CHALLENGES; DIGITAL CONTROLLERS; DIGITAL CONTROLS; HIGH RESOLUTION DPWM; IMPROVED PERFORMANCE; LIMIT CYCLING; LOW COSTS; NON LINEARITIES; OSCILLATION AMPLITUDES; RAMP DESIGN; SYSTEM PERFORMANCES; VOLTAGE-MODE CONTROL;

POWER ELECTRONICS;

EID: 49249115462     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEC.2008.4522857     Document Type: Conference Paper

References (20)

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