An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn 3, Issue , 2005, Pages 1412-1418

  Foley, Raymond F ^a   Kavanagh, Richard C ^a   Marnane, William P ^a   Egan, Michael G ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; NATURAL FREQUENCIES; POWER ELECTRONICS; WAVEFORM ANALYSIS;

DIGITAL PULSEWIDTH MODULATION; FREQUENCY CALIBRATION; OUTPUT WAVEFORMS;

PULSE WIDTH MODULATION;

EID: 33646506301     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEC.2005.1453214     Document Type: Conference Paper

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