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Volumn 18, Issue 8, 2008, Pages 566-568

ROM-based direct digital synthesizer at 24 GHz clock frequency in InP DHBT technology

Author keywords

Accumulator; Digital to analog converter (DAC); Direct digital synthesizer (DDS); Emitter coupled logic (ECL); Heterojunction bipolar transistor (HBT); High speed integrated circuits; Indium Phosphide (InP); Read only memory (ROM)

Indexed keywords

BIPOLAR TRANSISTORS; DIGITAL ARITHMETIC; HETEROJUNCTION BIPOLAR TRANSISTORS; TECHNOLOGY; TRANSISTORS;

EID: 49249106149     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2008.2001025     Document Type: Article
Times cited : (28)

References (9)
  • 3
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    • Direct digital synthesis for enabling next generation RF systems
    • Nov
    • K. R. Elliott, "Direct digital synthesis for enabling next generation RF systems," in CSIC Dig., Nov. 2005, pp. 125-128.
    • (2005) CSIC Dig , pp. 125-128
    • Elliott, K.R.1
  • 4
    • 33646400609 scopus 로고    scopus 로고
    • Direct digital synthesizer with ROM-less architecture at 13-GHz clock frequency in InP DHBT technology
    • May
    • S. E. Turner and D. E. Kotecki, "Direct digital synthesizer with ROM-less architecture at 13-GHz clock frequency in InP DHBT technology," IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 296-298, May 2006.
    • (2006) IEEE Microw. Wireless Compon. Lett , vol.16 , Issue.5 , pp. 296-298
    • Turner, S.E.1    Kotecki, D.E.2
  • 5
    • 33749506451 scopus 로고    scopus 로고
    • Direct digital synthesizer with sine-weighted DAC at 32-GHz clock frequency in InP DHBT technology
    • Oct
    • S. E. Turner and D. E. Kotecki, "Direct digital synthesizer with sine-weighted DAC at 32-GHz clock frequency in InP DHBT technology," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2284-2290, Oct. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.10 , pp. 2284-2290
    • Turner, S.E.1    Kotecki, D.E.2
  • 7
    • 0023996587 scopus 로고
    • A GaAs 4 bit adder-accumulator circuit for direct digital synthesis
    • Apr
    • C. G. Eckroot and S. I. Long, "A GaAs 4 bit adder-accumulator circuit for direct digital synthesis," IEEE J. Solid-State Circuits, vol. SSC-23, no. 2, pp. 573-580, Apr. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.SSC-23 , Issue.2 , pp. 573-580
    • Eckroot, C.G.1    Long, S.I.2
  • 8
    • 15844379193 scopus 로고    scopus 로고
    • 4 bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology
    • Mar
    • S. E. Turner, R. B. Elder Jr., D. S. Jansen, and D. E. Kotecki, "4 bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology," IEEE Microw. Wireless Compon. Lett., vol. 15, no. 3, pp. 144-146, Mar. 2005.
    • (2005) IEEE Microw. Wireless Compon. Lett , vol.15 , Issue.3 , pp. 144-146
    • Turner, S.E.1    Elder Jr., R.B.2    Jansen, D.S.3    Kotecki, D.E.4
  • 9
    • 33847765067 scopus 로고    scopus 로고
    • 36-GHz, 16 × 6 bit ROM in InP DHBT technology suitable for DDS application
    • Feb
    • S. Manandhar, S. E. Turner, and D. E. Kotecki, "36-GHz, 16 × 6 bit ROM in InP DHBT technology suitable for DDS application," IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 451-456, Feb. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.2 , pp. 451-456
    • Manandhar, S.1    Turner, S.E.2    Kotecki, D.E.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.