On the yield of compiler-based eSRAMs

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2004, Pages 11-19

  Wang, X ^a   Ottavi, M ^b   Meyer, F ^c   Lombardi, F ^b  

^a IBM   (United States)

^b NORTHEASTERN UNIVERSITY   (United States)

^c Wichita State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC CHIPS; ESRAM; MEMORY ARCHITECTURE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; PRODUCT DESIGN; PROGRAM COMPILERS; REDUNDANCY;

STATIC RANDOM ACCESS STORAGE;

EID: 24944457384     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347820     Document Type: Conference Paper

References (13)

1. I. Koren and Z. Koren, Defect Tolerant VLSI Circuits: Techniques and Yield Analysis, Proceedings of the IEEE, Vol. 86, pp. 1817-1836, Sept. 1998.
2. X. Wang, M. Ottavi and F. Lombardi. "Yield Analysis of Compiler-based Arrays of Embedded SRAMs" pp. 3-10, Proc. of IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, 2003.
3. C. H. Stapper, A. N. Mclaren, and M. Dreckmann, "Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product." IBM J. Res. Develop., vol.24, no.3, pp.398-409, 1980.
4. R. M. Warner, "Applying a Composite Model to the IC Yield Problem". IEEE Journal of Solid State Circuits., vol.SC-9, no.3, pp.86-95, June 1974.
5. C. H. Stapper, "On Murphy's Yield Integral". IEEE Trans. Semiconductor Manufacturing, vol.4, no.4, pp.294-297, Nov. 1991.
6. C. H. Stapper, "On yield, fault distributions and clustering of particles." IBM J. Res. Develop., vol.30, no.3, pp.326-338, May, 1986.
7. C. H. Stapper, "Large-Area Fault Clusters and Fault Tolerance in VLSI Ciruits" IBM J. Res. Develop., vol.33, no.2, pp.162-173, March 1989.
8. C. H. Stapper, "Small-Area Fault Clusters and Fault Tolerance in VLSI Ciruits" IBM J. Res. Develop., vol.33, no.2, pp.174-177, March 1989.
9. C. H. Stapper, "Improved Yield Model for fault-Tolerant Memory Chips". IEEE Tan. on Computers, vol.42, no.7, pp.872-881, July 1993.
10. GA Allen, "A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation," Proc. of IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, 1998, pp. 4452.
11. www-3.ibm.com/chips/products/asics/products/ememory.html
12. IBM, on-line document, ASIC Memory Compiler, 2002.
13. IBM, on-line document of ASIC Dept, 2002.