-
1
-
-
27944492851
-
A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations
-
T. Shibata and T. Ohmni, "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," IEEE Transactions on Electron Devices 39, 1992.
-
(1992)
IEEE Transactions on Electron Devices
, vol.39
-
-
Shibata, T.1
Ohmni, T.2
-
3
-
-
0035047219
-
Overview of floating-gate devices, circuits and systems
-
January
-
P. Hasler, T. S. Lande, "Overview of floating-gate devices, circuits and systems," IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, Vol.48, No. 1, January 2001.
-
(2001)
IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing
, vol.48
, Issue.1
-
-
Hasler, P.1
Lande, T.S.2
-
4
-
-
0035301001
-
Low-power CMOS with subvolt supply voltages
-
April
-
M. R. Stan, "Low-power CMOS with subvolt supply voltages," IEEE Transactions on VLSI Systems, Vol.9, No.2, April 2001.
-
(2001)
IEEE Transactions on VLSI Systems
, vol.9
, Issue.2
-
-
Stan, M.R.1
-
5
-
-
0035052130
-
-
E. Rodríguez-Villegas, G. Huertas, M. J. Avedillo, J. M. Quintana and A. Rueda, A Practical Floating-Gate Muller-C Element Using vMOS Thershold Gates, IEEE Transactions on Cirucits and Systems-II: Analog and Digital Signal Processing, 48, No.1, January 2001.
-
E. Rodríguez-Villegas, G. Huertas, M. J. Avedillo, J. M. Quintana and A. Rueda, "A Practical Floating-Gate Muller-C Element Using vMOS Thershold Gates," IEEE Transactions on Cirucits and Systems-II: Analog and Digital Signal Processing, Vol. 48, No.1, January 2001.
-
-
-
-
6
-
-
0000651840
-
A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits
-
S.Aunet, Y. Berg, T. Ytterdal, Ø. Næss, T. Sæther, "A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits," The 8th IEEE International conference on Electronics, Circuits and Systems, Vol.2, pp. 1035-1038, 2001.
-
(2001)
The 8th IEEE International conference on Electronics, Circuits and Systems
, vol.2
, pp. 1035-1038
-
-
Aunet, S.1
Berg, Y.2
Ytterdal, T.3
Næss, Ø.4
Sæther, T.5
-
7
-
-
0036294819
-
-
K. Rahimi, C. Diorio, C. Hernandez and M.D. Brockhausen, A simulation model for floating-gate MOS synapse transistors, ISCAS2002, Proc. of the 2002 IEEE International Sympposium on Circuits and Systems, 2, pp. 532-535, May 2002.
-
K. Rahimi, C. Diorio, C. Hernandez and M.D. Brockhausen, "A simulation model for floating-gate MOS synapse transistors," ISCAS2002, Proc. of the 2002 IEEE International Sympposium on Circuits and Systems, Vol.2, pp. 532-535, May 2002.
-
-
-
-
8
-
-
12144285857
-
Very low-voltage analog signal processiing based on quasi-floating gate transistors
-
March
-
J. Ramírez-Angulo, A.J. López-Martín, R. González Carvajal and F. Muñoz Chavero, "Very low-voltage analog signal processiing based on quasi-floating gate transistors," IEEE Journal of Solid-State Circuits. Vol. 39, No. 3, pp. 434-442, March 2004.
-
(2004)
IEEE Journal of Solid-State Circuits
, vol.39
, Issue.3
, pp. 434-442
-
-
Ramírez-Angulo, J.1
López-Martín, A.J.2
González Carvajal, R.3
Muñoz Chavero, F.4
-
9
-
-
0030396735
-
Ultra-Low-Power CMOS Technologies, Invited paper
-
G. Schrom and S. Selberherr, "Ultra-Low-Power CMOS Technologies," Invited paper, Proc. of International Semiconductor Conference. Vol. 1, pp. 237-246, 1996.
-
(1996)
Proc. of International Semiconductor Conference
, vol.1
, pp. 237-246
-
-
Schrom, G.1
Selberherr, S.2
-
10
-
-
0242423715
-
Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS,
-
Ph.D. Dissertation, Norwegian University of Science and Technology, Trondheim, Norway
-
S. Aunet, "Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS," Ph.D. Dissertation 2002:52, Norwegian University of Science and Technology, Trondheim, Norway, 2002.
-
(2002)
, pp. 52
-
-
Aunet, S.1
-
11
-
-
0003850954
-
-
ISBN 0-13-120764-4, pp, Second edition, Prentice Hall
-
J. M. Rabaey, "Digital Integrated Cirucuits - A design perspective", ISBN 0-13-120764-4, pp. 188-193, Second edition, Prentice Hall, 2003.
-
(2003)
Digital Integrated Cirucuits - A design perspective
, pp. 188-193
-
-
Rabaey, J.M.1
-
12
-
-
24944509428
-
-
S. Aunet and V. Beiu, Ultra Low Power Fault Tolerant Neural Inspired CMOS Logic, ICJNN'05, Proc. of IEEE International Joint Conference on Neural Networks 2005, 5, pp.2843-2848, August 2005.
-
S. Aunet and V. Beiu, "Ultra Low Power Fault Tolerant Neural Inspired CMOS Logic," ICJNN'05, Proc. of IEEE International Joint Conference on Neural Networks 2005, Vol. 5, pp.2843-2848, August 2005.
-
-
-
|