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Volumn , Issue , 2007, Pages 314-317

Small fan-in floating-gate circuits with application to an improved adder structure

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS;

EID: 48349148523     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.143     Document Type: Conference Paper
Times cited : (4)

References (12)
  • 1
    • 27944492851 scopus 로고
    • A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations
    • T. Shibata and T. Ohmni, "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," IEEE Transactions on Electron Devices 39, 1992.
    • (1992) IEEE Transactions on Electron Devices , vol.39
    • Shibata, T.1    Ohmni, T.2
  • 4
    • 0035301001 scopus 로고    scopus 로고
    • Low-power CMOS with subvolt supply voltages
    • April
    • M. R. Stan, "Low-power CMOS with subvolt supply voltages," IEEE Transactions on VLSI Systems, Vol.9, No.2, April 2001.
    • (2001) IEEE Transactions on VLSI Systems , vol.9 , Issue.2
    • Stan, M.R.1
  • 5
    • 0035052130 scopus 로고    scopus 로고
    • E. Rodríguez-Villegas, G. Huertas, M. J. Avedillo, J. M. Quintana and A. Rueda, A Practical Floating-Gate Muller-C Element Using vMOS Thershold Gates, IEEE Transactions on Cirucits and Systems-II: Analog and Digital Signal Processing, 48, No.1, January 2001.
    • E. Rodríguez-Villegas, G. Huertas, M. J. Avedillo, J. M. Quintana and A. Rueda, "A Practical Floating-Gate Muller-C Element Using vMOS Thershold Gates," IEEE Transactions on Cirucits and Systems-II: Analog and Digital Signal Processing, Vol. 48, No.1, January 2001.
  • 7
    • 0036294819 scopus 로고    scopus 로고
    • K. Rahimi, C. Diorio, C. Hernandez and M.D. Brockhausen, A simulation model for floating-gate MOS synapse transistors, ISCAS2002, Proc. of the 2002 IEEE International Sympposium on Circuits and Systems, 2, pp. 532-535, May 2002.
    • K. Rahimi, C. Diorio, C. Hernandez and M.D. Brockhausen, "A simulation model for floating-gate MOS synapse transistors," ISCAS2002, Proc. of the 2002 IEEE International Sympposium on Circuits and Systems, Vol.2, pp. 532-535, May 2002.
  • 10
    • 0242423715 scopus 로고    scopus 로고
    • Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS,
    • Ph.D. Dissertation, Norwegian University of Science and Technology, Trondheim, Norway
    • S. Aunet, "Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS," Ph.D. Dissertation 2002:52, Norwegian University of Science and Technology, Trondheim, Norway, 2002.
    • (2002) , pp. 52
    • Aunet, S.1
  • 12
    • 24944509428 scopus 로고    scopus 로고
    • S. Aunet and V. Beiu, Ultra Low Power Fault Tolerant Neural Inspired CMOS Logic, ICJNN'05, Proc. of IEEE International Joint Conference on Neural Networks 2005, 5, pp.2843-2848, August 2005.
    • S. Aunet and V. Beiu, "Ultra Low Power Fault Tolerant Neural Inspired CMOS Logic," ICJNN'05, Proc. of IEEE International Joint Conference on Neural Networks 2005, Vol. 5, pp.2843-2848, August 2005.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.