Very low-voltage analog signal processing based on quasi-floating gate transistors

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 3, 2004, Pages 434-442

  Ramírez Angulo, Jaime ^a   López Martín, Antonio J ^b   González Carvajal, Ramón ^c   Muñoz Chavero, Fernando ^c  

^a New Mexico State University   (United States)

^b PUBLIC UNIVERSITY OF NAVARRE   (Spain)

^c UNIVERSITY OF SEVILLE   (Spain)

Author keywords

Amplifiers; Analog CMOS circuits; Analog integrated circuits; Analog processing circuits; CMOS analog integrated circuits; Digital to analog conversion; Low voltage CMOS circuits; Quasi floating gate transistors; Sample and hold circuits

Indexed keywords

CAPACITANCE MEASUREMENT; CAPACITORS; CMOS INTEGRATED CIRCUITS; EQUIVALENT CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS; POWER CONVERTERS; VOLTAGE MEASUREMENT; WAVEFORM ANALYSIS;

ANALOG INTEGRATED CIRCUITS; LOW VOLTAGE ANALOG SIGNAL PROCESSING; PROGRAMMABLE GAIN AMPLIFIER; QUASI FLOATING GATE TRANSISTOR;

MOSFET DEVICES;

EID: 12144285857     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.822782     Document Type: Article

References (14)

1. S. Yan and E. Sanchez-Sinencio, "Low voltage analog circuit design: A tutorial," IEICE Trans. Analog Integrated Circuits and Systems, vol. E83A, no. 2, pp. 179-196, Feb. 2000.
2. J. Ramírez-Angulo, S. C. Choi, and G. González-Altamirano, "Low-voltage OTA architectures using multiple input floating gate transistors," IEEE Trans. Circuits Syst. II, vol. 2, pp. 971-974, Nov. 1995.
3. J. Ramírez-Angulo and A. Lopez, "MITE circuits: The continuous time counterpart to switched capacitor circuits," IEEE Trans. Circuit Syst. II, vol. 48, pp. 45-55, Jan. 2001.
4. W. P. Millard, Z. K. Kalyjian, and A. Andreou, "Calibration and matching of floating gate devices," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Geneva, May 2000, pp. IV 389-392.
5. C. Urquidi, J. Ramírez-Angulo, R. González-Carvajal, and A. Torralba, "A new family of low-voltage circuits based on quasi-floating gate transistors," in Proc. IEEE Midwest Symp. Circuits Syst. (MWSCAS), Tulsa, OK, Aug. 2002, pp. I93-96.
6. V. Koosh and R. Goodman, "Dynamic charge restoration of floating-gate subthreshold MOS translinear circuits," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Sydney, Australia, May 2001, pp. I33-36.
7. J. Crols and M. Steyaert, "Switch-Opamp: An approach to realize full CMOS switched-capacitor circuits at very low voltage supply voltages," IEEE J. Solid-State Circuits, vol. 29, pp. 936-942, Aug. 1994.
8. M. A. Abo and P. R. Gray, "A 1.5 V, 10-bit, 14.3 MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
9. T. L. Brooks, D. H. Robertson, D. F. Kelly, A. Del Muro, and S. W. Harston, "A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR," IEEE J. Solid-State Circuits, vol. 32, pp. 1896-1900, Dec. 1997.
10. J. Ramírez-Angulo, C. Urquidi, R. González-Carvajal, A. Torralba, and A. López-Martín, "A new family of very low voltage analog circuits based on quasi-floating gate transistors," IEEE Trans. Circuits Syst. II, vol. 50, pp. 214-220, May 2003.
11. J. Ramírez-Angulo, "Compact single 1.5 V supply four quadrant analog CMOS multiplier using multiple input floating gate transistors," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Neuchatel, Switzerland, Sept. 1996, pp. 99-103.
12. J. F. Schoeman and T. H. Joubert, "Four quadrant analogue CMOS multiplier using capacitively coupled dual-gate transistors," Electron. Lett., vol. 32, no. 3, pp. 209-210, Feb. 1996.
13. A. Baschirotto, "A low-voltage sample-and-hold circuit in standard CMOS technology operating at 40 Ms/s," IEEE Trans. Circuits Syst. II, vol. 48, pp. 394-399, Apr. 2001.
14. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proc. IEEE, vol. 84, pp. 1584-1614, Nov. 1996.