Embedded support vector machine: Architectural enhancements and evaluation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 685-690

  Dey, Soumyajit ^a   Kedia, Monu ^a   Agarwal, Niket ^a   Basu, Anupam ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL ENHANCEMENTS; ARCHITECTURAL MODIFICATIONS; CLASSIFICATION TASKS; CLASSIFICATION TECHNIQUES; EMBEDDED PROCESSOR ARCHITECTURES; FUTURE GENERATIONS; INTELLIGENT EMBEDDED DEVICES; MACHINE LEARNINGS; PERFORMANCE IMPROVEMENTS; RECOGNITION TASKS; RESEARCH AND DEVELOPMENTS; STATE OF THE ARTS; SUPPORT VECTORS;

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; GEARS; IMAGE RETRIEVAL; INFORMATION MANAGEMENT; INTEGRATED CIRCUITS; LEARNING SYSTEMS; MILITARY PHOTOGRAPHY; MULTILAYER NEURAL NETWORKS; ROBOT LEARNING; SUPPORT VECTOR MACHINES; VECTORS;

EMBEDDED SYSTEMS;

EID: 48349137956     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.73     Document Type: Conference Paper

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