A power estimation model for an FPGA-based softcore processor

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 171-176

  Zipf, Peter ^a   Hinkelmann, Heiko ^a   Deng, Lei ^a   Glesner, Manfred ^a   Blume, Holger ^b   Noll, Tobias G ^b  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

^b RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; BENCHMARKING; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

FUNCTION BLOCKS; FUNCTIONAL LEVEL POWER ANALYSES; INSTRUCTION LEVELS; MEASURED DATUMS; MEASURED RESULTS; POWER ANALYSIS; POWER CONSUMPTIONS; POWER ESTIMATIONS; PROCESSOR MODELS; SOFTCORE PROCESSORS; SPECIFIC POWER CONSUMPTIONS; SYSTEM DESIGN FLOWS; TEST SCENARIOS;

MODAL ANALYSIS;

EID: 48149110001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380643     Document Type: Conference Paper

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