Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

Journal of Systems Architecture

Volumn 53, Issue 10, 2007, Pages 689-702

  Blume, H ^a   Becker, D ^a   Rotenberg, L ^a   Botteck, M ^b   Brakensiek, J ^b   Noll, T G ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

^b NOKIA   (Germany)

Author keywords

Embedded processors; Modeling accuracy; Power estimation

Indexed keywords

CODES (SYMBOLS); COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DIGITAL FILTERS; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS;

EMBEDDED PROCESSORS; FUNCTIONAL LEVEL POWER ANALYSIS (FLPA); MODELING ACCURACY; POWER ESTIMATION;

PROGRAM PROCESSORS;

EID: 34248536304     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2007.01.002     Document Type: Article

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