Wafer level hermetic packaging of MOEMS devices

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2007, Pages 294-297

  Yang, Charles ^a   Xu, Antai ^a   Wang, Ye ^a  

^a Miradia   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANODIC BONDING; CHIP-LEVEL; CMOS-MEMS; COST MANUFACTURING; DIE SIZE; ELECTRONICS MANUFACTURING; FINE TUNING; GLASS FRITS; HERMETIC PACKAGING; HIGH YIELD; LOW TEMPERATURES; MEMS DEVICES; MEMS PACKAGING; MICRO MIRROR DEVICES; MICRO MIRRORS; MICRO-OPTO-ELECTRO-MECHANICAL SYSTEMS; MONOLITHICALLY INTEGRATED; PHYSICAL CONTACTS; TRANSPARENT SUBSTRATES; WAFER SIZES; WAFER-LEVEL HERMETIC PACKAGING; WAFER-LEVEL PACKAGING;

CHIP SCALE PACKAGES; CHLORINE COMPOUNDS; COMPOSITE MICROMECHANICS; ELECTRONIC EQUIPMENT MANUFACTURE; GLASS; GLASS BONDING; MEMS; MICROELECTROMECHANICAL DEVICES; MIRRORS; MONOLITHIC INTEGRATED CIRCUITS; NONMETALS; OPTICAL DESIGN; SILICON; SILICON WAFERS; SUBSTRATES; TECHNOLOGY; WAFER BONDING;

ELECTRONICS PACKAGING;

EID: 48149086395     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMT.2007.4417080     Document Type: Conference Paper

References (4)

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2. T. M. H. Lee, D. H. Y. Lee, C. Y. N. Liaw, A. I. K. Lao, I. M. Hsing, "Detailed characterization of anodic bonding process between glass and thin-film coated silicon substrates", Sensors and Actuators A-Physical, 86, 2000, pp 103-107.
3. D. Sparks, S. Massoud-Ansari, and N. Najafi, "Long-term evaluation of hermetically glass frit sealed silicon to Pyrex wafers with feedthroughs", J. Micromech. Microeng. 15, 2005, pp 1560-1564.
4. R. Knechtel, "Glass frit bonding: an universal technology for wafer level encapsulation and packaging", Microsyst. Technol., 12, 2005, pp 63-68.