Formal model construction using HDL simulation semantics

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2007, Pages 115-122

  Buck, Joseph ^a   Wang, Dong ^a   Zhu, Yunshan ^b  

^a SYNOPSYS INC   (United States)

^b NONE

Author keywords

HDL simulation semantics; Symbolic simulation; Transaction level equivalence checking

Indexed keywords

COMPLEXATION; COMPUTATIONAL METHODS; DIGITAL SIGNAL PROCESSING; INDUSTRIAL ENGINEERING; INFORMATION THEORY; LINGUISTICS; MACHINE DESIGN; QUERY LANGUAGES; SEMANTICS; TESTING;

CLOCK CYCLES; FORMAL MODELING; FORMAL VERIFICATIONS; GATED CLOCKS; HARDWARE DESCRIPTION LANGUAGE (VHDL); HARDWARE VERIFICATION; HIGH LEVEL DESIGNS; INDUSTRIAL DESIGNS; INTERNATIONAL (CO); KRIPKE STRUCTURES; LANGUAGE SEMANTICS; NEW APPROACHES; SAMPLE POINTS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 47949090405     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2007.4392797     Document Type: Conference Paper

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