DRAM simulator for design and analysis of digital systems

Microprocessors and Microsystems

Volumn 26, Issue 4, 2002, Pages 189-198

  Alakarhu, Juha ^a   Niittylahti, Jarkko ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

DRAM; Memory system; Performance evaluation; Simulation

Indexed keywords

BANDWIDTH; CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PACKET NETWORKS;

DIGITAL SYSTEMS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0037007532     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0141-9331(02)00013-3     Document Type: Article

References (12)

1. Evaluating DRAM performance with various cache configurations
2. Rascas access
3. Memory bandwidth limitations of future microprocessors
4. A performance comparison of contemporary DRAM architectures
5. Reducing DRAM latencies with an integrated memory hierarchy design
6. Incorporating DRAM access modes into high-level synthesis